Coreless Signal Distribution Structure for Thinner Semiconductor Packages
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Solution Overview
Problem
Current semiconductor packages and methods for forming them, such as those using interposer technology with through-silicon vias, face challenges including excess cost, decreased reliability, and large package sizes.
Innovation Solution
A semiconductor package utilizing a coreless signal distribution structure, which comprises at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface, allowing for the bonding of semiconductor dies without a core support, and a method of manufacturing this package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposer technology with through-silicon vias is used, then signal distribution is achieved, but package size becomes large and cost increases
Solution Approach 1:
The patent removes the traditional core support structure (interposer) from the signal distribution system. By extracting this unnecessary component, the package size is reduced while maintaining signal distribution functionality through alternative means (conductive layers and dielectric structures without through-silicon vias).
Solution Approach 2:
The patent implements signal distribution through localized conductive layers and dielectric structures rather than a global interposer framework. This allows signal paths to be created in specific areas where needed, eliminating the need for a comprehensive through-silicon via system and reducing overall package volume.
2Reliability
If interposer technology with through-silicon vias is used, then signal distribution is achieved, but manufacturing cost increases
Solution Approach 1:
By removing the interposer and through-silicon via structures, the patent eliminates complex manufacturing steps associated with drilling, filling, and planarizing deep vias through silicon substrates. This extraction of unnecessary components directly reduces manufacturing cost while preserving signal distribution capability.
Solution Approach 2:
The patent changes the structural parameters of the signal distribution system by eliminating the core support and through-silicon vias. This parameter change simplifies the manufacturing process and reduces material requirements, thereby lowering production costs while maintaining functional performance.
3Stability of the object's composition
If core support structure is used, then structural stability is provided, but package thickness increases
Solution Approach 1:
The patent extracts the core support structure (interposer) that traditionally provided structural stability. By removing this thickening component, the package thickness is reduced while structural integrity is maintained through alternative design elements such as reinforced dielectric layers and optimized conductive structures.
Solution Approach 2:
The patent employs thin film structures (conductive layers and dielectric films) to provide the necessary structural support without the bulk of traditional core supports. These thin films maintain structural stability while minimizing thickness contribution to the overall package.
Data Source
AI summary
A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.