Coreless Signal Distribution Structure for Thin Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor packages face issues with excess cost, decreased reliability, and large package sizes due to limitations in interposer technology, leading to inadequate performance in multi-dimensional packaging and through-silicon vias.
Innovation Solution
A semiconductor package utilizing a coreless signal distribution structure with conductive and dielectric layers, which eliminates the need for through-silicon vias and printed circuit boards, enabling smaller linewidths and reduced thickness by forming a redistribution structure with conductive layers and dielectric layers on a wafer without a core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interposer technology with through-silicon vias is used, then electrical connections between semiconductor dies can be established, but manufacturing cost increases and reliability decreases
Solution Approach 1:
The patent removes the core substrate from the signal distribution structure, eliminating the need for through-silicon vias and complex interposer technology. This extraction of the core element simplifies the manufacturing process, reduces costs, and improves reliability by removing potential failure points associated with TSV formation and core-substrate interfaces.
Solution Approach 2:
The patent transitions from a conventional planar PCB-like structure with through-vias to a layered signal distribution structure where conductive patterns are formed on dielectric layers without requiring vertical through-holes. This dimensional reorganization eliminates the need for TSVs while maintaining electrical connectivity functionality.
2Length of stationary object
If through-silicon vias and printed circuit boards are used, then signal distribution is achieved, but package thickness increases
Solution Approach 1:
By removing the core substrate and eliminating through-silicon vias, the patent significantly reduces the vertical dimension of the package. The signal distribution function is maintained through conductive patterns on dielectric layers, achieving thin-profile packaging without sacrificing electrical connectivity.
Solution Approach 2:
The patent employs thin dielectric layers with integrated conductive patterns to replace thick PCB structures. This approach enables signal distribution in a thin-film format, reducing overall package thickness while maintaining the necessary electrical interconnection capabilities.
3Ease of manufacture
If conventional signal distribution structures with cores are used, then structural support is provided, but manufacturing complexity and cost increase
Solution Approach 1:
The patent eliminates the core substrate entirely, relying on the semiconductor dies themselves and the encapsulant material to provide structural support. This removal of the core simplifies manufacturing by eliminating core preparation, TSV formation, and core-to-die attachment processes, while the encapsulant provides the necessary mechanical support for the thin-film signal distribution structure.
Solution Approach 2:
The encapsulant material serves multiple functions: it provides structural support replacing the core, protects the signal distribution layers, and enables the thin-film architecture. This multi-functionality allows the removal of the core without compromising structural integrity.
Data Source
AI summary
A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.