Coreless Signal Distribution Structure for Thinner Multi-Die Packaging
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes due to inadequate interposer technology, particularly in multi-dimensional packages.
Innovation Solution
A semiconductor package utilizing a coreless signal distribution structure with conductive and dielectric layers, which eliminates the need for through-silicon vias and printed circuit boards, allowing for smaller linewidths and reduced thickness, and enables electrical connections between semiconductor dies with different pattern widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interposer technology with through-silicon vias is used, then electrical connections between semiconductor dies can be established, but manufacturing cost increases and package size becomes too large
Solution Approach 1:
The patent extracts and eliminates the through-silicon via structure from the interposer, replacing it with a coreless signal distribution approach using only conductive and dielectric layers. This removes the bulky via holes and associated complex manufacturing processes while maintaining electrical connection functionality between semiconductor dies.
Solution Approach 2:
The interposer is segmented into distinct functional layers: conductive layers for signal distribution, dielectric layers for insulation and mechanical support, and optional encapsulant layers for protection. This segmentation allows each layer to be optimized independently, reducing overall package size while maintaining connection reliability.
2Reliability
If conventional interposer technology with through-silicon vias is used, then electrical connections can be established, but manufacturing cost increases
Solution Approach 1:
The patent extracts the expensive through-silicon via manufacturing process and replaces it with simpler conductive layer deposition techniques. This eliminates costly TSV formation steps including drilling, plating, and filling operations, significantly reducing manufacturing cost while maintaining electrical connection reliability.
Solution Approach 2:
The patent employs standard semiconductor fabrication processes for creating conductive and dielectric layers that are already part of typical chip manufacturing workflows. These processes are more cost-effective and scalable compared to specialized TSV fabrication, making the interposer more economically viable.
3Reliability
If through-silicon vias are used in the interposer, then signal distribution is achieved, but the package thickness increases
Solution Approach 1:
The patent removes the through-silicon via structure that adds vertical thickness, replacing signal distribution with planar conductive layers. This eliminates the need for deep via holes penetrating the interposer, significantly reducing package thickness while maintaining effective signal routing between dies.
Solution Approach 2:
The patent transitions from three-dimensional through-silicon via signal paths to two-dimensional planar conductive layer signal distribution. This dimensional change allows signal routing to occur within the plane of the interposer rather than requiring vertical penetration, thereby reducing overall package thickness.
Data Source
AI summary
A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.