Coreless Package Substrate Ceramic Stiffener
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Solution Overview
Problem
Conventional flip chip packages face limitations in increasing layout density due to the difficulty in reducing the pitch of plating through holes (PTHs), which restricts the advancement of substrate interconnection density.
Innovation Solution
A coreless package substrate with a ceramic stiffener is introduced, eliminating PTHs and featuring a ceramic stiffener with higher strength to reduce residual stress and warp, allowing for increased wiring density and additional electronic component placement areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If plating through holes (PTHs) are used in the substrate interconnection structure, then electrical connection between layers is achieved, but the pitch cannot be reduced further which limits layout density
Solution Approach 1:
The patent extracts and eliminates the plating through holes (PTHs) from the substrate interconnection structure. By removing this limiting component, the invention achieves higher wiring density without the pitch constraints that previously existed with PTH-based interconnection methods.
2Quantity of substance
If the substrate layout density is increased, then more electrical connections are possible, but residual stress and warp increase affecting co-planarity
Solution Approach 1:
The patent introduces a ceramic stiffener integrated with the organic substrate to form a composite structure. The ceramic material provides high stiffness and dimensional stability, counteracting the residual stress and warp that occur when wiring density is increased, thereby maintaining co-planarity of the substrate.
3Strength
If conventional metal stiffener is used, then structural support is provided, but warp occurs during fabrication and residual stress remains
Solution Approach 1:
The patent changes the material parameter from metal to ceramic for the stiffener. This material substitution fundamentally alters the mechanical properties, providing superior stiffness and thermal stability that prevent warp during fabrication and eliminate residual stress, thereby achieving better manufacturing precision and warp control.
Data Source
AI summary
A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.


