Coreless Thin Substrate with Embedded Chip and Heat Sink
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Solution Overview
Problem
Conventional multi-chip package modules have a thicker structure and longer electrical transmission paths, leading to increased vulnerability to cross-talk interference and reduced packaging density.
Innovation Solution
A thermally enhanced coreless thin substrate with an embedded chip, featuring a patterned carrier metal layer with a heat sink portion, a dielectric layer, and a wiring layer that integrates the chip, heat sink, and electrical connections, reducing thickness and enhancing heat dissipation and sealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional laminate or build-up technique is used to fabricate the substrate, then the substrate can be manufactured with standard processes, but the resulting multi-chip package module has a thicker structure and longer electrical transmission paths
Solution Approach 1:
The patent merges the substrate structure with the chip package components into an integral thin board type electronic device. The carrier substrate integrates the function of both the printed circuit board and the chip carrier, eliminating the need for separate laminate construction and reducing overall package thickness.
Solution Approach 2:
The patent transitions from a conventional thick laminate structure to a thin board type structure by changing the dimensional approach. The carrier substrate uses a thin flexible or rigid support with conductive patterns formed directly on it, rather than building up multiple laminated layers, thereby reducing the thickness dimension.
2Adaptability or versatility
If conventional separate manufacturing of circuit board and chip package is used, then manufacturing flexibility is maintained, but the electrical transmission paths become longer and more vulnerable to cross-talk
Solution Approach 1:
The patent combines the circuit board and chip package into a single integrated carrier substrate structure. The conductive patterns on the carrier substrate provide both mechanical support and electrical interconnection, reducing transmission path length and minimizing cross-talk between adjacent signal traces.
3Device complexity
If conventional chip packaging is used without integrated heat sink, then assembly simplicity is maintained, but heat dissipation capacity is insufficient
Solution Approach 1:
The patent integrates the heat sink function directly into the carrier substrate structure. The conductive patterns on the carrier substrate serve dual purposes as both electrical interconnects and thermal management pathways, conducting heat away from the embedded chips without requiring separate heat sink components.
Solution Approach 2:
The carrier substrate performs multiple functions simultaneously: it provides mechanical support, electrical interconnection, and thermal management. The conductive patterns serve both as circuit traces for signal transmission and as heat conduction paths for thermal dissipation, eliminating the need for separate dedicated heat sink structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in improved assembling ability, interconnection reliability, electrical performance, and reduced cross-talk interference, while minimizing package thickness and increasing packaging density.
Implementation Method 1
The patterned carrier metal layer inside the substrate includes at least one heat sink portion
Data Source
AI summary
A thermally enhanced coreless thin substrate with embedded chips, which mainly includes a patterned carrier metal layer, at least one chip, at least one dielectric layer and at least one wiring layer, is disclosed. The chip is attached to a heat sink portion of the patterned carrier metal layer. The dielectric layer is formed over the patterned carrier metal layer and covers the chip. The wiring layer is formed on the dielectric layer for electrically connecting the patterned carrier metal layer and the chip. In the process of manufacturing the thermally enhanced coreless thin substrate with embedded chips, the heat sink portion is formed by patterning the patterned carrier metal layer after finishing the formation of the wiring layer. Thus, a thin board type electronic device that combines a heat sink, a carrier substrate and embedded chips together to form an integral unit is fabricated.