Coreless Substrate Embedded Die Package Assembly
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving compact, high-performance designs with mixed technology die stacking and package stacking capabilities while maintaining a thin profile, and they require costly assembly processes.
Innovation Solution
A semiconductor package with a coreless substrate that embeds the die, eliminating conventional flip-chip assembly steps and enabling mixed-technology die stacking or package stacking, reducing assembly costs and allowing for full panel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional flip-chip assembly is used, then electrical interface is provided, but assembly costs increase and assembly complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-attaching the die to the substrate using wire-bonding interconnects before final package assembly. This eliminates the need for costly and complex flip-chip assembly processes later, as the die is already in place and electrically connected. The wire-bonding is performed in advance during substrate fabrication, simplifying subsequent assembly steps.
Solution Approach 2:
The patent extracts the die from the traditional flip-chip assembly process and embeds it directly into the substrate during substrate fabrication. This separation of the die attachment step from the final assembly process reduces both cost and complexity by using simpler wire-bonding technology instead of expensive flip-chip bonding equipment and processes.
2Length of stationary object
If coreless substrate is used, then packaging profile is reduced, but support for mixed technology die stacking is limited
Solution Approach 1:
The patent applies universality by designing the coreless substrate with a universal architecture that can accommodate multiple die types and stacking configurations. The substrate includes multiple die cavities and interconnect structures that support both wire-bonded and flip-chip mounted dies, as well as multiple stacking levels, all within a thin profile. This multi-functional design enables mixed-technology die stacking without requiring different substrate types.
Solution Approach 2:
The patent transitions from a conventional two-dimensional substrate layout to a three-dimensional stacked architecture. By embedding dies vertically within the substrate thickness and providing interconnects between multiple stacking levels, the design achieves high integration density in the vertical dimension while maintaining a thin overall packaging profile. This dimensional transition enables mixed-technology stacking capability.
3Device complexity
If die is embedded in substrate, then assembly steps are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by performing die attachment and wire-bonding operations during the substrate fabrication process itself, before final package assembly. This early integration allows for precise die placement and bonding under controlled fabrication conditions, reducing the precision demands on subsequent assembly steps. The die is embedded and connected in advance when manufacturing equipment provides highest precision.
Data Source
AI summary
Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.


