Single Layer Coreless Substrate With Glass Fiber Dielectric
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Solution Overview
Problem
Existing chip packaging technologies, such as lead frames and multilayer substrates, face issues with reliability due to warping, bending, and the risk of wire breakage or shorting, particularly in single-layer configurations, which affect the mechanical support and electrical performance of integrated circuit chips.
Innovation Solution
A novel chip packaging solution involving a chip bonded to a routing layer and a via post layer surrounded by a dielectric material with glass fibers in a polymer resin, where the chip and routing layers are embedded in a second dielectric layer, and optionally featuring a metallic sacrificial base and non-cylindrical via posts, to enhance stiffness and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer coreless substrate configuration is used, then the device complexity and manufacturing cost are reduced, but the mechanical support and warping resistance are insufficient
Solution Approach 1:
The patent uses a composite structure combining a coreless substrate with a dielectric layer containing glass fiber mats. The glass fibers provide mechanical reinforcement and warping resistance while the coreless design maintains simplicity and cost-effectiveness. This resolves the contradiction by integrating materials with complementary properties rather than adding structural complexity.
2Volume of moving object
If the substrate is made thinner to reduce package size, then the volume and weight are reduced, but the stiffness and mechanical support are compromised
Solution Approach 1:
The dielectric layer incorporates glass fiber mats that provide high stiffness-to-weight ratio. This allows the substrate to be made thinner while maintaining adequate mechanical support through the reinforced dielectric material rather than increasing overall substrate thickness.
3Reliability
If traditional multilayer substrates with via posts are used, then the electrical performance and reliability are improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
The patent extracts the via posts from the substrate structure, creating a coreless design where the dielectric layer itself serves as the primary support structure. This eliminates complex via formation processes while maintaining electrical performance through alternative interconnection methods, thereby reducing manufacturing cost and process complexity.
Solution Approach 2:
The substrate is segmented into functional layers with the dielectric layer containing glass fiber mats providing mechanical support independent of the electrical interconnection structure. This separation allows optimization of each layer for its specific function without requiring complex integration of support and electrical functions.
4Stability of the object's composition
If lead frame technology is used for mechanical support, then the structural stability is ensured, but the wire breakage risk and shorting potential increase
Solution Approach 1:
The patent removes the lead frame structure entirely, replacing it with a coreless substrate design where the dielectric layer with glass fiber mats provides mechanical support. This eliminates the rigid lead frame that causes wire stress and potential breakage, while maintaining structural stability through the flexible yet strong composite dielectric structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides a cost-effective, high-performance chip package that is thinner and more reliable than traditional multilayer substrates, with reduced risk of wire breakage and improved thermal performance, while maintaining electrical integrity.
Implementation Method 1
a dielectric material with glass fibers in a polymer resin
Implementation Method 2
via post layer surrounded by a dielectric material
Implementation Method 3
chip bonded to a routing layer of an interposer comprising a routing layer
Implementation Method 4
dielectric material with glass fibers in a polymer resin
Data Source
AI summary
An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.