Coreless Substrate Integrated Circuit Packaging
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in reducing package size while maintaining reliability and manufacturing yield, and are pressured by commercial demands for increased functionality and cost reduction.
Innovation Solution
The method involves providing a semiconductor die with exposed contacts, depositing an insulation layer, applying a conductive layer, and coupling system interconnects to the conductive layer for electrical connection, allowing for a compact and reliable packaging system with enhanced thermal management features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If package size is reduced to meet commercial demands, then space efficiency improves, but manufacturing yield and reliability deteriorate
Solution Approach 1:
The patent transitions from a conventional substrate-based packaging approach to a coreless architecture where the semiconductor die is directly mounted on the package substrate. This dimensional reorganization eliminates the substrate core volume, allowing for smaller package size while maintaining adequate manufacturing yield and reliability through direct die-substrate integration.
Solution Approach 2:
The patent extracts and removes the substrate core from the traditional packaging structure, creating a coreless substrate design. This extraction eliminates unnecessary material and space, reducing overall package size while improving manufacturing efficiency and reliability by simplifying the packaging architecture.
2Volume of moving object
If package size is reduced, then space efficiency improves, but long term reliability deteriorates
Solution Approach 1:
By reorganizing the packaging structure to eliminate the substrate core and adopt a coreless design, the patent achieves smaller package volume while extending long-term reliability. The direct mounting architecture reduces thermal paths and mechanical stress points, thereby improving durability despite the reduced size.
Solution Approach 2:
The removal of the substrate core simplifies the packaging structure, reducing the number of interfaces and potential failure points. This extraction leads to a more robust design that maintains long-term reliability while achieving compact dimensions.
3Adaptability or versatility
If functionality is increased to meet commercial demands, then device capability improves, but package complexity increases
Solution Approach 1:
The coreless substrate package design provides a universal platform that can accommodate multiple semiconductor dies and support various interconnection technologies. This multi-functional architecture enables increased device capability without proportionally increasing package complexity, as the same basic structure can be scaled and configured for different applications.
Solution Approach 2:
The patent employs advanced interconnection techniques such as through-substrate vias and three-dimensional stacking, which add functionality by utilizing vertical and lateral dimensions rather than increasing planar complexity. This allows multiple functions to be integrated in a compact, organized manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a flexible, high-volume platform for integrating multiple functions, including thermal management, while reducing package size and maintaining reliability, thus addressing the commercial pressures for smaller, more functional, and cost-effective integrated circuit products.
Implementation Method 1
depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed
Implementation Method 2
applying a conductive layer on the semiconductor die contacts and the insulation layer
Data Source
AI summary
An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.