Coreless Packaging Substrate Metal Bumps with Exposed Wing Portions
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Solution Overview
Problem
Conventional coreless packaging substrates face challenges with increased thickness due to core boards, alignment difficulties between solder balls and openings, reduced bonding force, and limited layout density due to larger metal bump areas and increased spacing between electrical pads.
Innovation Solution
A method of fabricating a coreless packaging substrate by forming electrical pads on both surfaces of a carrier board, embedding conductive elements, forming metal bumps with exposed wing portions, and using a dielectric passivation layer to ensure complete exposure of metal bump surfaces for direct chip mounting, eliminating the need for openings and enhancing bonding force and layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If openings are formed on the solder mask to expose electrical pads, then solder balls can be connected to electrical pads, but alignment difficulty increases and manufacturing complexity increases
Solution Approach 1:
The patent removes the solder mask layer from specific regions to directly expose the electrical pads, eliminating the need for openings in the solder mask. This extraction approach allows solder balls to be directly connected to electrical pads without alignment issues, as the pads are naturally exposed rather than requiring precise opening formation.
Solution Approach 2:
Instead of forming openings in the solder mask to expose pads (conventional approach), the patent inverts the approach by removing the solder mask itself in specific areas, allowing the pads to be directly accessible. This reversal eliminates the alignment problem between openings and pads.
2Reliability
If openings are formed on the solder mask to expose electrical pads, then solder balls can be connected to electrical pads, but the process complexity increases
Solution Approach 1:
The patent extracts the solder mask layer from specific regions where electrical pads are located, eliminating the need for complex opening formation processes. This simplifies the manufacturing process by removing unnecessary steps while maintaining reliable electrical connections.
3Productivity
If metal bump area is reduced to improve layout density, then more pads can be arranged, but bonding force between metal bumps and chips decreases
Solution Approach 1:
The patent employs a composite structure for metal bumps consisting of a solder material layer and a copper layer. The solder material provides bonding functionality while the copper layer enhances mechanical strength and bonding force. This composite approach allows reduced bump area for higher layout density while maintaining sufficient bonding strength through the multi-layer structure.
Data Source
AI summary
A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.