Coreless Substrate Packaging for Compact IC Integration
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in reducing package size while maintaining reliability and manufacturing yield, and are pressured by commercial demands for increased functionality and cost reduction.
Innovation Solution
The method involves depositing a top trace on a manufacturing carrier, attaching discrete components, mounting vias separated from the components, and forming a dielectric layer to create a component surface, with system interconnects for electrical connection, allowing for a flexible and high-volume integration of multiple functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If package size is reduced to meet commercial demand for smaller products, then space efficiency improves, but manufacturing yield and reliability deteriorate
Solution Approach 1:
The substrate is divided into multiple separate dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with conductive traces and vias distributed across different levels. This segmentation allows the package to maintain compact overall dimensions while providing sufficient space for reliable component placement and electrical connections, thereby improving manufacturing yield without sacrificing space efficiency.
Solution Approach 2:
The patent utilizes three-dimensional routing with conductive traces on different dielectric layers connected through vias (first vias, second vias, third vias). This vertical dimensionality allows electrical connections to be established without increasing the horizontal package footprint, enabling reduced package size while maintaining reliable signal paths and component placement areas.
2Adaptability or versatility
If more functions are integrated into smaller space, then functionality increases, but manufacturing complexity increases
Solution Approach 1:
The substrate structure with multiple dielectric layers and conductive traces serves multiple functions simultaneously: it provides mechanical support, establishes electrical connections between components, routes signals across different functional blocks, and enables thermal management. This multi-functionality allows diverse electronic functions to be integrated without proportionally increasing manufacturing complexity, as the same structural elements fulfill multiple roles.
3Ease of manufacture
If cost reductions are implemented to meet commercial pressure, then manufacturing cost decreases, but long term reliability deteriorates
Solution Approach 1:
The patent incorporates preliminary design features such as pre-planned via locations, pre-defined trace routing paths across dielectric layers, and pre-allocated component placement areas. These preliminary actions are built into the substrate structure during manufacturing, enabling cost-effective high-volume production while ensuring reliable electrical connections and component integration. The modular layered structure allows for standardized manufacturing processes that reduce cost without compromising long-term reliability.
Data Source
AI summary
An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.