Coreless Semiconductor Substrate with Embedded Photoactive Traces
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Solution Overview
Problem
Conventional semiconductor packaging methods, such as layer-by-layer buildup on a glass reinforced core or coreless processes using organic substrates, face limitations in routing density and are costly due to the need for seed layer removal and high electrical resistivity.
Innovation Solution
A coreless substrate structure is formed with photoactive dielectric layers and embedded traces, eliminating the need for seed layer removal and allowing for finer routing patterns without capture pads, thereby improving routing density and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If layer-by-layer buildup on glass reinforced core is used, then structural support is provided, but routing density is insufficient
Solution Approach 1:
The patent removes the glass reinforced core from the substrate structure, transitioning from a core-based architecture to a coreless architecture. This extraction eliminates the structural support constraint that limited routing density, allowing traces to be routed more densely without the interference of a central core material.
Solution Approach 2:
The patent embeds traces within the dielectric layers rather than routing them on the surface or through a core structure. This dimensional reorganization allows traces to be positioned in three-dimensional space within the substrate layers, enabling higher routing density by utilizing the vertical dimension and eliminating the need to route around a central core.
2Manufacturing precision
If coreless process with organic substrates is used, then finer routing is achieved, but cost increases due to seed layer removal
Solution Approach 1:
The patent uses a temporary photoactive dielectric layer that serves as a sacrificial placeholder during manufacturing. This temporary layer is removed after serving its purpose of enabling trace formation, eliminating the need for costly seed layer removal processes while maintaining fine routing capability. The temporary layer is a low-cost material that can be easily deposited and removed.
Solution Approach 2:
The photoactive dielectric layer acts as an intermediary material that facilitates trace formation during manufacturing. It serves as a temporary placeholder that enables the deposition and patterning of conductive traces, then is removed after serving its mediating function. This intermediary approach avoids the need for expensive seed layers and their subsequent removal.
3Manufacturing precision
If fab-like processes with thin copper routing layer are used, then very fine routing is achieved, but electrical resistivity increases
Solution Approach 1:
The patent changes the parameters of the conductive traces by using thicker copper traces formed through electroplating rather than thin sputtered copper layers. The electroplating process allows for controlled deposition of copper at greater thicknesses, maintaining low electrical resistivity while achieving fine routing through precise pattern definition in the photoactive dielectric layer.
Solution Approach 2:
The patent replaces the sputtering process with electroplating for copper trace formation. Sputtering is a physical vapor deposition process that produces thin layers, while electroplating is an electrochemical process that can deposit thicker, more conductive copper layers. This substitution maintains fine routing capability through photoresist patterning while achieving lower electrical resistivity through thicker copper deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves lower height profiles, cost savings, and higher routing density by embedding traces within dielectric layers and using padless vias, enhancing manufacturing efficiency and reducing the profile of bump pads compared to conventional devices.
Implementation Method 1
laminating a top of the core with a photoactive (photoimageable) dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer
Implementation Method 2
plating the plurality of trace patterns to form a plurality of traces
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.