Coreless Wiring Substrate Build-Up for Fine-Pitch Interconnects
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Solution Overview
Problem
Existing methods for manufacturing wiring substrates face challenges in achieving high-density wiring with fine widths and inter-wiring distances, particularly in the formation of conductor layers and insulating layers, which can lead to misalignment and reduced yield in the manufacturing process.
Innovation Solution
A method involving direct imaging exposure is used to form resist patterns for conductor layers, allowing for the creation of fine wirings with minimum widths and inter-wiring distances, and the use of insulating layers without core materials to facilitate the formation of via conductors at a fine pitch, resulting in a coreless wiring substrate with improved connection reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional exposure methods are used to form resist patterns for conductor layers, then the manufacturing process is simpler, but the wiring width and inter-wiring distance cannot be sufficiently reduced
Solution Approach 1:
The patent replaces conventional photomask-based optical exposure with direct imaging exposure technology, substituting a mechanical/optical system with a more advanced direct imaging system capable of achieving finer resolution (10 µm or less) for resist patterns, thereby enabling reduced wiring width and inter-wiring distance
2Manufacturing precision
If core materials are included in insulating layers, then the insulating layers have better mechanical strength, but via conductor formation at fine pitch becomes difficult
Solution Approach 1:
The patent extracts and removes core materials from the insulating layers, creating coreless insulating layers that enable precise via conductor formation at fine pitch (10 µm or less) while maintaining sufficient mechanical strength through alternative reinforcement methods
Solution Approach 2:
The patent applies different structural characteristics to different regions: the insulating layers are coreless in areas requiring fine via conductor pitch, while support substrates provide localized mechanical strength where needed, achieving both precision and strength requirements
3Manufacturing precision
If fine wiring patterns are formed in conductor layers, then high-density wiring is achieved, but misalignment in the manufacturing process increases
Solution Approach 1:
The patent replaces conventional photomask alignment methods with direct imaging exposure technology that achieves superior alignment accuracy of 5 µm or less, enabling high-density wiring patterns without increased misalignment errors in the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the production of high-density wirings with superior resolution and reduced process complexity, enhancing the manufacturing yield and connection reliability of the wiring substrate.
Implementation Method 1
exposing the first resist layer by direct imaging exposure
Data Source
AI summary
A method for manufacturing a wiring substrate includes preparing two support substrates having one or more product areas, forming a first build-up part including first conductor and insulating layers across the one or more product areas on a first surface of each support substrate, positioning the substrates such that second surfaces of the substrates face each other, and forming a second build-up part including second conductor and insulating layers on each first build-up part. The minimum wiring width and the minimum inter-wiring distance of wirings in the first conductor layers are smaller than those of wirings in the second conductor layers. The forming the first build-up part includes forming a first resist layer having a first resist pattern and forming a conductor pattern according to the first resist pattern for each first conductor layer. The forming the first resist layer includes exposing the first resist layer by direct imaging exposure.