Coreless Single-Layer Wiring Package Substrate Fabrication
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Solution Overview
Problem
Conventional package substrates with core layers face challenges in reducing overall thickness due to complex fabrication processes and the need for conductive vias, which hinder miniaturization and low-profile requirements in electronic devices.
Innovation Solution
A package substrate is fabricated without a core layer, featuring a single wiring layer embedded in a dielectric body with exposed surfaces, allowing direct electrical connection to semiconductor components, and using photosensitive materials to simplify the process and eliminate the need for mechanical drilling or laser drilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a core layer with multiple wiring layers is used, then electrical connection between wiring layers is achieved, but the substrate thickness cannot be reduced and fabrication complexity increases
Solution Approach 1:
The patent removes the core layer from the substrate structure, extracting only the essential wiring layer while eliminating the thick core layer that prevented thickness reduction. This allows the substrate to achieve low-profile thickness while maintaining electrical connection functionality through the single exposed wiring layer.
Solution Approach 2:
Instead of forming conductive vias through the core layer to connect wiring layers (conventional approach), the patent inverts the approach by exposing the wiring layer directly through the dielectric body without requiring through-holes or vias, thereby eliminating the thickness constraint imposed by the core layer.
2Reliability
If conductive vias are formed through mechanical drilling or laser drilling, then electrical connection between wiring layers is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent extracts and eliminates the conductive via formation process entirely by removing the core layer requirement. Electrical connection is achieved directly through the exposed wiring layer surface, eliminating mechanical drilling, laser drilling, and electroplating processes.
Solution Approach 2:
The patent replaces the mechanical drilling and laser drilling systems with a simpler dielectric removal process that directly exposes the wiring layer, substituting complex mechanical/optical systems with a more straightforward fabrication approach.
3Strength
If a core layer is used in the package substrate, then structural support is provided, but the overall thickness of the package structure cannot be reduced
Solution Approach 1:
The patent extracts the core layer from the substrate structure, removing the thick structural support element that prevented thickness reduction. The dielectric body is optimized to provide necessary support while maintaining low-profile thickness, enabling the package structure to meet low-profile requirements.
4Quantity of substance
If multiple wiring layers are stacked with conductive vias, then wiring density is increased, but fabrication complexity and substrate thickness increase
Solution Approach 1:
The patent transitions from vertical stacking of multiple wiring layers connected by vias to a single wiring layer with enhanced in-plane wiring density. This dimensional shift from vertical to horizontal wiring organization achieves high wiring density without increasing substrate thickness or fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall thickness of the package substrate, simplifies the fabrication process, and increases wiring density without the need for conductive vias, enabling smaller electronic devices with improved reliability and reduced production costs.
Implementation Method 1
In an embodiment, the dielectric body is made of a photosensitive dielectric material.
Data Source
AI summary
A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.