Corner Gate Structure for Epitaxial Growth and Short Prevention
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Solution Overview
Problem
In integrated circuit fabrication, conductive contacts to raised source or drain terminals near the corner of semiconductor material can penetrate thinner portions, leading to undesirable connections with the substrate, causing structural defects and electrical shorts.
Innovation Solution
A gate structure is designed to entirely cover the edge and corner segment of the semiconductor region, with varying widths and masking materials to constrain epitaxial growth and prevent contacts from penetrating the substrate, ensuring proper surface area and preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an electrically inactive gate is placed at the edge of semiconductor material to provide a physical boundary, then epitaxial growth and silicide formation are controlled, but conductive contacts to raised source or drain terminals may penetrate thinner portions of semiconductor material near the inactive gate, directly connecting to the substrate in undesirable areas
Solution Approach 1:
The gate structure is segmented into active and inactive portions, with the inactive gate positioned at the edge to control epitaxial growth while the active gate maintains electrical integrity. This segmentation allows different regions of the gate to perform different functions without interfering with each other.
Solution Approach 2:
A silicide region is introduced as an intermediary layer between the conductive contact and the substrate. This silicide region prevents direct penetration of the conductive contact through the semiconductor material, thereby maintaining electrical connection integrity while allowing the inactive gate to control epitaxial growth.
2Ease of manufacture
If conductive contacts are formed to raised source or drain terminals, then electrical connections are established, but the contacts may penetrate thinner portions of semiconductor material and create undesirable connections to the substrate
Solution Approach 1:
A silicide region serves as an intermediary barrier between the conductive contact and the substrate. This intermediate layer allows easy formation of electrical connections to the raised source or drain terminals while preventing harmful direct penetration to the substrate.
Solution Approach 2:
The silicide region is formed in advance before the conductive contacts are deposited. This preliminary action creates a protective barrier that prevents subsequent contacts from penetrating the semiconductor material, thereby eliminating the harmful effect before it can occur.
3Ease of operation
If the semiconductor material thickness is reduced near the inactive gate to allow contact formation, then conductive contacts can be formed to raised terminals, but the reduced thickness causes direct connection to the substrate in undesirable areas
Solution Approach 1:
The silicide region acts as an intermediary that allows conductive contacts to access the raised terminals while maintaining electrical isolation from the substrate. This intermediary layer resolves the conflict between contact accessibility and electrical isolation by providing a controlled interface.
Solution Approach 2:
The semiconductor structure exhibits local quality variations, with different regions having different properties. The silicide region is locally positioned at the interface between the contact and substrate, providing enhanced electrical isolation precisely where needed, while allowing other regions to maintain their original characteristics for optimal device performance.
Data Source
AI summary
Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.