Semiconductor Package Pad Layout for Reliable Stacked Connections
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Solution Overview
Problem
Semiconductor packages face challenges in achieving reliable connections between stacked packages while maintaining compact size and high data processing capacity, with existing technologies struggling to ensure consistent and robust inter-package connections.
Innovation Solution
The semiconductor package design incorporates a first semiconductor package with a redistribution layer, a molded member, and a wiring structure featuring upper pads and connection bumps, along with a vertical connection structure that electrically connects the redistribution layer to the pads, and a second semiconductor package with lower redistribution pads, utilizing specific pad and bump configurations to enhance connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection bumps are made larger to improve electrical connection reliability between stacked packages, then connection reliability is improved, but the device complexity and manufacturing precision requirements increase
Solution Approach 1:
The patent applies different pad widths and bump sizes at different locations on the wiring structure. Corner pads have larger widths and correspond to larger connection bumps, while central pads have smaller dimensions. This local differentiation optimizes connection reliability at critical corner positions while maintaining overall package compactness, resolving the contradiction between reliability improvement and device complexity.
2Reliability
If pad sizes are increased to ensure robust electrical connections, then connection reliability is improved, but the area occupied by pads increases reducing the compactness of the package
Solution Approach 1:
The patent implements non-uniform pad sizing where corner pads are larger and central pads are smaller. This local quality differentiation ensures robust electrical connections at corner positions which are more critical for package stability, while minimizing the total pad area by reducing sizes at central positions, thus resolving the contradiction between connection reliability and package compactness.
Solution Approach 2:
The patent creates an asymmetric pad layout where corner pads have different dimensions compared to central pads. This asymmetric configuration optimizes the distribution of connection reliability across the package surface, placing larger pads where mechanical and electrical stress is highest (corners) while using smaller pads in less critical areas (center), thereby achieving reliable connections with minimal total area.
Data Source
AI summary
A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.