Corrective Read with Partial Block Offset in Memory Devices
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Solution Overview
Problem
Existing memory sub-systems face challenges in accurately reading data from memory cells due to physical phenomena like charge loss, which cause threshold voltage shifts, leading to errors, especially in partially programmed blocks where default read offsets are inadequate.
Innovation Solution
Implementing corrective read operations with partial block offset by determining the state of adjacent wordlines and applying specific read voltage offsets, either partial or full block optimized, to accurately read memory cells and reduce error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If default read operations are used in partially programmed blocks, then read speed is maintained, but data accuracy deteriorates due to charge loss and threshold voltage shifts
Solution Approach 1:
The patent implements dynamic read operations that adaptively adjust read voltages and offsets based on the programming state of adjacent wordlines. The system determines whether adjacent wordlines are programmed or erased and selectively applies different read parameters (default, partial block, or full block offsets) to optimize data accuracy for each specific scenario, resolving the contradiction between maintaining simple default reads and achieving accurate reads in partially programmed blocks
Solution Approach 2:
The patent changes read operation parameters (voltages and offsets) based on the detected state of adjacent wordlines. By monitoring adjacent wordline states and dynamically selecting appropriate read offsets (default, partial block, or full block), the system adjusts parameters to compensate for charge loss effects, thereby improving data accuracy without requiring complete re-reading of all blocks
2Measurement precision
If corrective read operations with adjacent wordline analysis are implemented, then data accuracy improves, but read time increases
Solution Approach 1:
The patent segments the read operation into distinct phases: determining adjacent wordline states, selecting appropriate read offsets based on those states, and executing the corrective read only where needed. This segmentation allows the system to apply complex corrective measures selectively rather than uniformly across all reads, improving data accuracy while minimizing the time penalty by avoiding unnecessary corrective operations in fully programmed blocks
Solution Approach 2:
The patent applies partial block offsets selectively based on the programming state of adjacent wordlines. Rather than always applying full corrective measures, the system uses partial offsets only when adjacent wordlines are in specific states (e.g., erased), thereby achieving sufficient data accuracy improvement without the complete time cost of exhaustive corrective reads in all scenarios
3Reliability
If uniform read offsets are applied to all blocks, then device complexity is minimized, but error rates increase in partially programmed blocks
Solution Approach 1:
The patent applies different read offsets (default, partial block, or full block) to different regions or scenarios based on the programming state of adjacent wordlines. Instead of using a uniform offset for all reads, the system tailors the read parameters to the local conditions of each block, thereby reducing error rates in partially programmed blocks while maintaining simplicity in fully programmed blocks through the use of default offsets
Data Source
AI summary
Control logic in a memory device receives a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of a memory array of a memory device and determines whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state. Responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state, the control logic identifies a partial block read voltage offset value and causes a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline.