Parallel Correlated-Bit Decoding for Higher LDPC Throughput
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Solution Overview
Problem
Conventional communication systems using LDPC codes face limitations in handling correlated data, leading to inefficient error correction and high computational complexity, especially in applications with stringent size and power constraints, as they typically perform bit-by-bit decoding and do not support concurrent error correction on multiple data bits or varying code rates.
Innovation Solution
A parallel iterative decoding system is introduced, which includes multiple modules for channel detection, updating, and estimation to process groups of correlated data bits concurrently, generating probability vectors and feedback signals to improve decoding efficiency and handle correlated data effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional LDPC decoders perform bit-by-bit decoding, then the decoding process is simple to implement, but the computational complexity increases and bit-throughput decreases when handling correlated data
Solution Approach 1:
The patent segments correlated data bits into groups of X bits and processes each group as a unit rather than individually. This segmentation allows the decoder to handle multiple correlated bits simultaneously through group-based probability vector operations, increasing bit-throughput while maintaining manageable complexity through structured processing of divided data units.
Solution Approach 2:
The patent transitions from bit-by-bit processing to group-based processing by introducing probability vectors of length 2^X that represent joint probabilities of X correlated bits. This dimensional change from scalar bit values to vector-based group representations enables concurrent processing of multiple bits, improving throughput while the structured vector operations keep implementation complexity controlled.
2Device complexity
If conventional LDPC decoders process data sequentially, then the implementation is straightforward, but the power consumption increases and processing time increases for error correction
Solution Approach 1:
The decoder structure is segmented into N parallel channel detection modules, N parallel updating modules, and N parallel decoding modules, where each module processes a group of X correlated bits simultaneously. This parallel segmented architecture reduces processing time by executing multiple operations concurrently while maintaining a structured implementation that manages complexity through modular design.
Solution Approach 2:
The patent merges channel detection, probability vector updating, and decoding operations into an integrated parallel processing framework where N modules operate simultaneously on N groups of correlated bits. This merging of functions into a unified parallel architecture reduces overall processing time compared to sequential execution while keeping the structure organized and implementable.
3Reliability
If conventional decoders use standard LDPC coding, then the error correction capability is adequate, but the coding gain is insufficient for applications with stringent power and size constraints
Solution Approach 1:
The patent changes the processing parameters from individual bit probabilities to joint probability vectors of X correlated bits, where each vector captures the statistical relationships among X bits. This parameter change enables more efficient error correction by exploiting correlation structure, improving reliability while reducing the computational resources and power needed compared to treating each bit independently with standard LDPC coding.
Data Source
AI summary
A decoding system for a communication channel includes N parallel channel detection modules that generate N first probability vectors based on sequences of X correlated bits in each of N groups of correlated bits, respectively. N parallel updating modules generate M second probability vectors based on the N first probability vectors and N feedback signals. N parallel estimation modules generate estimates of the X correlated bits in each of the N groups of correlated bits based on the M second probability vectors. N parallel decoding modules generate the N feedback signals and N output signals based on the estimates of the X correlated bits in each of the N groups of correlated bits. X is an integer greater than one, M is an integer greater than or equal to one, and N is an integer greater than or equal to M.