Correlated Double Sampling Counter for Image Sensor Signal Subtraction
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Solution Overview
Problem
Existing correlated double sampling techniques require separate memories and subtractor modules to subtract pixel reset and sensor signals, which can be complex and inefficient.
Innovation Solution
Implementing a counter-controlled system that uses 2's complement arithmetic to generate the data value by setting all bits to 1, incrementing during a first period, inverting bits, and incrementing again during a second period to subtract the pixel reset and sensor signals, eliminating the need for separate memories and subtractor modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memories and subtractor modules are used to implement correlated double sampling, then the measurement function is achieved, but the device complexity increases
Solution Approach 1:
The patent combines the memory function and subtractor function into a single counter unit. The counter stores the first measurement value, then automatically performs the subtraction operation when the second measurement value is input, eliminating the need for separate memory and subtractor modules while maintaining the correlated double sampling measurement function.
Solution Approach 2:
The counter unit is designed to perform multiple functions: it acts as a memory element to store the first measurement value, and simultaneously functions as a subtractor to compute the difference between the first and second measurement values. This multi-functional design reduces the overall device complexity while achieving the required measurement capability.
2Measurement precision
If separate memories and subtractor modules are used, then the measurement accuracy is maintained, but the manufacturing cost and device complexity increase
Solution Approach 1:
By merging the memory and subtractor functions into a single counter unit, the patent reduces the number of discrete components that need to be manufactured and assembled. This integration simplifies the manufacturing process, reduces assembly steps, and lowers production costs while preserving the measurement accuracy through the counter's precise digital operation.
3Device complexity
If a counter-based system is used to eliminate separate memories and subtractors, then the device complexity is reduced, but the operational precision must be maintained
Solution Approach 1:
The counter unit is designed to automatically perform the subtraction operation without requiring external control logic. When the second measurement value is input, the counter automatically subtracts it from the stored first measurement value and outputs the result. This self-service capability ensures precise measurement operations while maintaining simplicity in the overall device architecture.
Data Source
AI summary
Apparatus and a method for correlated double sampling using an up-counter for parallel image sensors. All bits of a counter are set to one. An offset signal is compared to a first reference signal to define a first period during which the counter is incremented. After the first period, all bits of the counter are inverted. A sensor signal is compared to a second reference signal to define a second period during which the counter is incremented to generate a correlated double sampling value.