Correlated Double Sampling Circuit Using Dual Capacitors
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Solution Overview
Problem
Current correlated double sampling (CDS) methods, particularly OPAMP-based subtraction methods, are vulnerable to power, area, and noise limitations, and the capacitive voltage divider in AC-coupled CDS systems restricts noise performance and speed.
Innovation Solution
A sampling circuit and method that utilize two capacitors and switches to sample and subtract reset and signal voltages, allowing for cancellation of common charge noise, with tunable capacitance and reference voltage control for level shifting and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If AC-coupled CDS with capacitive voltage divider is used, then reset noise can be removed, but noise performance and speed are limited due to large CDS capacitor requirements
Solution Approach 1:
The patent divides the CDS operation into two separate sampling phases using two distinct capacitors (first capacitor for reset voltage, second capacitor for signal voltage). This segmentation allows each capacitor to be optimized independently, eliminating the need for a large single CDS capacitor and improving both noise performance and speed.
Solution Approach 2:
The patent transitions from a single-capacitor AC-coupled approach to a dual-capacitor architecture with separate sampling paths. This dimensional change in the circuit topology enables simultaneous optimization of noise performance and sampling speed without the trade-offs inherent in the traditional capacitive voltage divider approach.
2Ease of operation
If OPAMP-based subtraction methods are used for CDS, then signal processing can be achieved, but power consumption and circuit area increase
Solution Approach 1:
The patent replaces the OPAMP-based subtractor (an active electronic system requiring power) with a passive charge subtraction mechanism. By directly connecting the two capacitors through a switch and utilizing charge redistribution, the system achieves subtraction functionality without active components, dramatically reducing power consumption.
Solution Approach 2:
The capacitors perform the subtraction operation autonomously through charge redistribution when connected. The system uses its own stored charges to automatically compute the difference without requiring external active processing elements, eliminating the need for powered OPAMPs while maintaining signal processing capability.
3Ease of operation
If OPAMP-based subtraction methods are used for CDS, then signal processing can be achieved, but circuit area increases
Solution Approach 1:
The patent replaces the bulky OPAMP-based subtractor circuit with a compact switch-based charge redistribution mechanism. This substitution eliminates the need for large active components and associated biasing circuits, significantly reducing the overall circuit area while preserving the essential CDS signal processing function.
4Object-affected harmful factors
If large CDS capacitor is used in AC-coupled CDS, then reset noise can be sampled, but the capacitor is difficult to drive and noise performance is not optimal
Solution Approach 1:
The patent segments the noise sampling function across two smaller capacitors rather than requiring one large capacitor. Each capacitor can be easily driven by standard circuit elements, and together they provide the necessary sampling capability without the drivability issues associated with large single capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces kTC noise and improves signal-to-noise ratio by canceling common charge noise, offering improved noise performance, power efficiency, and area reduction while enabling flexible level shifting.
Implementation Method 1
a reset switch electrically connected with its first node to the input node, and electrically connected with its second node to a first node of a first capacitor, a sampling switch electrically connected with its first node to the input node, and electrically connected with its second node to a first node of a second capacitor
Implementation Method 2
a first switch electrically connected between the second node of the first capacitor and the first node of the second capacitor, a second switch electrically connected between the first node of the first capacitor the second node of the second capacitor
Data Source
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AI summary
A circuit (100) for correlated double sampling, comprising: a reset switch (120) connected with an input node (110A), and with a first node (130A) of a first capacitor (130); a sampling switch (140) connected with the input node (110A), and with a first node (150A) of a second capacitor (150); a second node (130B, 150B) of the first/second capacitor (130, 150) is adapted to be connected with a first/second reference node (110B, 110C), of which at least one using a reference switch (160); a first switch (171) connected between the second node (130B) of the first capacitor (130) and the first node (150A) of the second capacitor (150); a second switch (172) connected between the first node (130A) of the first capacitor (130) and the second node (150B) of the second capacitor (150).