Correlated Multi-Pass Programming for Nonvolatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programming techniques for non-volatile memory devices require numerous verify operations, especially for multi-state cells, leading to increased programming time and reduced performance as the number of distinguishable state levels increases, due to the need for multiple sensing operations and fine programming pulse step sizes.
Innovation Solution
The implementation of correlated multi-pass programming, where memory cells are programmed in parallel with each pass using a staircase pulse train with a common step size and offset, reducing the number of programming pulses and verify operations by using a multiple-pass index programming method that maintains a program index for each cell to control programming voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional programming techniques are used with multiple verify operations, then programming accuracy is improved, but programming time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing a first programming pass that programs memory cells to a preliminary state before the final programming operation. This preliminary pass establishes initial threshold voltage levels that are then refined in subsequent passes, reducing the need for extensive verify operations in later stages and thereby decreasing total programming time while maintaining accuracy.
Solution Approach 2:
The patent segments the programming process into multiple distinct passes: a first programming pass that programs cells to a preliminary state, and a second programming pass that programs to the final state. This segmentation allows each pass to be optimized independently, with the first pass using coarser verification and the second pass using finer verification, thus reducing overall verification overhead.
2Quantity of substance
If the number of distinguishable state levels is increased, then storage capacity is improved, but the number of verify operations increases
Solution Approach 1:
By programming memory cells to a preliminary state in the first pass before final programming, the patent reduces the verification burden for multi-state cells. The preliminary programming establishes coarse threshold voltage levels that are then refined in the second pass, allowing multi-state cells to be programmed more efficiently without requiring full verification sequences for each state transition.
Solution Approach 2:
The patent employs dynamic verification strategies where the verification process adapts based on the programming pass stage. In the first programming pass, verification is performed with coarser granularity, while in the second pass, verification is refined. This dynamic approach allows the system to handle multi-state cells efficiently by adjusting verification intensity to match the programming stage requirements.
3Measurement precision
If fine programming pulse step sizes are used, then programming precision is improved, but the number of programming pulses increases
Solution Approach 1:
The patent segments the programming precision requirements across two passes: the first pass uses coarser programming pulse step sizes to reach preliminary threshold voltage levels, while the second pass uses finer pulse step sizes to achieve final precise threshold voltage levels. This segmentation allows the system to use fine precision only when necessary, reducing the total number of programming pulses required.
Solution Approach 2:
By performing preliminary programming with coarser pulse steps in the first pass, the patent reduces the range of threshold voltage adjustment needed in the second pass. This preliminary action allows the final programming pass to use finer pulse steps for shorter duration, thereby maintaining programming precision while reducing overall programming duration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of programming pulses and verify operations, improving programming performance and tightening the distribution of threshold voltages across memory states, particularly beneficial for devices storing three or more bits per cell.
Implementation Method 1
memory cells are programmed in parallel with each pass using a staircase pulse train with a common step size and offset
Data Source
AI summary
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses.