Correlated Double Sampler Circuit With Low-Capacitance Non-Interleaving
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Solution Overview
Problem
Existing semiconductor devices, such as amplifiers for sampling and amplifying input signals, face challenges in efficiently sampling and amplifying signals with low noise, particularly in CCD/CMOS image sensors and scanners, where interleaving architectures require higher input sampling capacitance.
Innovation Solution
A non-interleaving correlated double sampler circuit is introduced, which includes operational amplifiers, input and output capacitors, sampling and holding switches, and combined switches. This circuit performs operational amplifier offset calibration and samples and amplifies signals in one clock cycle without the need for specific clock signals, utilizing a non-interleaving architecture that saves input sampling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If interleaving architecture is used for signal sampling and amplification, then signal amplification capability is improved, but input sampling capacitance requirement increases
Solution Approach 1:
The circuit is divided into multiple non-interleaved phases (first phase for offset calibration, second phase for signal sampling and amplification) that operate sequentially rather than simultaneously. This segmentation allows each phase to be optimized independently, reducing the overall capacitance requirement while maintaining amplification capability.
Solution Approach 2:
The circuit employs periodic clock cycles to alternate between offset calibration phase and signal sampling/amplification phase. By using periodic action, the circuit reuses the same hardware components for different functions at different time periods, eliminating the need for higher capacitance that would be required in continuous interleaved operation.
2Measurement precision
If operational amplifier offset calibration is performed separately, then amplification precision is improved, but device complexity increases
Solution Approach 1:
The offset calibration function and signal sampling/amplification function are merged into a single circuit architecture that operates in different phases. The same operational amplifiers, switches, and capacitors are reused for both offset calibration and signal processing, reducing device complexity while maintaining precision through sequential operation.
Solution Approach 2:
The circuit components (operational amplifiers, switches, capacitors) are designed to serve multiple functions: during the first phase they perform offset calibration, and during the second phase they perform signal sampling and amplification. This multi-functionality reduces the overall number of components needed while maintaining high precision.
3Quantity of substance
If non-interleaving architecture is used, then input sampling capacitance is reduced, but signal processing speed may be affected
Solution Approach 1:
The circuit maintains continuous useful action by ensuring that while one phase is completing its operation, the next phase is prepared in advance. The periodic clocking ensures seamless transition between offset calibration and signal sampling phases, maintaining effective processing throughput despite the non-interleaved architecture.
Data Source
AI summary
A method of operating a circuit includes providing the circuit, the circuit including: an operational amplifier, having a first input terminal, a second input terminal, a first output terminal and a second output terminal. A first sampling switch is directly coupled to the first input terminal, a second sampling switch is directly coupled to the second input terminal, a third sampling switch is directly coupled to a first output end, and a fourth sampling switch is directly coupled to a second output end. A first holding switch is coupled to the first output terminal, and a second holding switch is coupled to the second output terminal. A first combined switch is coupled to a first input capacitor, and a second combined switch is coupled to a second input capacitor.