Corrugated Capacitor Structure for Low-Temperature BEOL Integration

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Solution Overview

Problem

The semiconductor industry faces challenges in developing capacitor structures that can be integrated in back-end-of-line (BEOL) processes without damaging previously fabricated front-end-of-line (FEOL) and middle-end-of-line (MEOL) devices, while also requiring advancements in integration density and material processing to support further miniaturization and functionality.

Innovation Solution

A capacitor structure is designed with a support structure featuring an alternating dielectric stack of first and second dielectric layers, a bottom electrode, a third dielectric layer, and a top electrode, where the first dielectric layers have a narrower width than the second, creating a corrugated profile, allowing for low-temperature processing and integration with thin film transistors (TFTs) without damaging existing devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional capacitor structures are integrated in BEOL processes, then integration density is improved, but previously fabricated FEOL and MEOL devices are damaged

Engineering Contradiction:

Improveintegration densityVSAvoiddevice integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the temperature parameter of the processing process, using low-temperature deposition and annealing processes (below 400°C) to form capacitor structures without damaging previously fabricated FEOL and MEOL devices, thus resolving the contradiction between integration density and device integrity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent segments the fabrication process into distinct low-temperature stages for forming the capacitor structure after FEOL and MEOL processes, allowing independent optimization of each stage's temperature profile to prevent damage to previously fabricated devices while achieving high integration density

Inventive Principle:

Principle #1Segmentation

2Productivity

If minimum feature size is reduced, then integration density is improved, but manufacturing precision becomes more difficult to maintain

Engineering Contradiction:

Improveintegration densityVSAvoidfeature size control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent replaces traditional high-temperature thermal processes with low-temperature atomic layer deposition (ALD) and plasma-based processes, enabling precise control of thin film thickness and composition at the nanometer scale without the thermal diffusion that complicates feature size control in conventional processes

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20240379735A1Capacitor structure and method of making the same

Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A disclosed method of manufacturing a capacitor structure includes forming an alternating dielectric stack comprising first dielectric layers and second dielectric layers on a substrate and forming a trench through the alternating stack of first dielectric layers and second dielectric layers. The disclosed method includes etching the first dielectric layers from the trench to form notches between the second dielectric layers and forming a bottom electrode layer covering the first dielectric layers and the second dielectric layers. The disclosed method includes forming a third dielectric layer over the bottom electrode layer and forming a top electrode layer over the third dielectric layer.