Cortex-M Coprocessor for CNN Acceleration
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Solution Overview
Problem
Current convolutional neural network (CNN) algorithms face inefficiency, high cost, and inflexibility in processor execution due to the limitations of typical microcontrol unit (MCU) processors, which struggle with massive data operations and require costly, inflexible hardware accelerators.
Innovation Solution
A convolutional neural network acceleration method and system utilizing a Cortex-M processor, where MCR and CDP instructions are set to configure internal registers and enable basic operators like convolution, Relu activation, pooling, and quantization, optimizing data operations and reducing hardware reconstruction costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated hardware accelerators are designed for CNN operations, then processing efficiency is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a coprocessor with a universal instruction set that can execute multiple CNN operations (convolution, pooling, activation functions, transposition) through a single hardware unit. The coprocessor uses configurable registers and a unified execution pipeline to handle different operations dynamically, eliminating the need for separate dedicated hardware accelerators for each operation type.
Solution Approach 2:
The coprocessor employs dynamic configuration through an instruction set architecture where operation parameters, data addresses, and execution modes are programmatically controlled. The hardware accelerator adapts its behavior based on incoming instructions, allowing the same physical hardware to reconfigure itself for different CNN layers and operations without physical redesign.
2Speed
If fixed hardware accelerator architectures are used, then processing speed is improved, but adaptability to diverse algorithms deteriorates
Solution Approach 1:
The coprocessor implements a universal instruction set that supports multiple CNN operations including convolution, pooling, various activation functions (Relu, Tanh, Sigmoid), transposition, and quantization. A single hardware unit can execute all these operations by interpreting different instructions, providing both high-speed processing and algorithmic diversity.
Solution Approach 2:
The coprocessor uses programmable parameters stored in configuration registers to adapt its operation. By changing register values and instruction parameters, the same hardware can process different data formats, precision requirements, and operation types, enabling flexible adaptation to diverse algorithms without sacrificing processing speed.
3Manufacturing precision
If custom hardware accelerators are tailored for specific algorithms, then processing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements a single coprocessor design that can achieve high processing precision for multiple different operations through software configuration rather than hardware customization. The unified architecture maintains consistent precision across convolution, pooling, and activation operations while using the same manufacturing process, reducing costs compared to multiple specialized hardware units.
4Device complexity
If standard MCU processors are used for CNN operations, then device complexity is reduced, but processing efficiency deteriorates
Solution Approach 1:
The patent introduces a coprocessor as an intermediary component between the standard MCU and the memory system. This coprocessor handles data-intensive CNN operations by providing specialized execution units and buffers, while the main MCU retains its general-purpose functionality. The coprocessor acts as a bridge that offloads computational tasks without requiring complete replacement of the standard processor architecture.
Data Source
AI summary
The application relates to a convolutional neural network acceleration method and system based on a Cortex-M processor, and a medium. The method comprises: setting a MCR instruction and a CDP instruction according to common basic operators of a convolutional neural network, the common basic operators comprising a convolution operator, a Relu activation operator, a pooling operator, a table look-up operator and a quantization operator; and configuring an internal register of a convolutional neural network coprocessor through the MCR instruction, and then enabling the common basic operators of the convolutional neural network through the CDP instruction. Through the application, problems of inefficiency, high cost and inflexibility of a cyclic neural network algorithm in the execution of a processor are solved, and the basic operators needed for the cyclic neural network to be executed through a coprocessor instruction set are realized.