Core-Oriented System Control Area for Multithreading Overhead Reduction

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Solution Overview

Problem

In multithreading environments, the management overhead increases substantially as the number of threads grows, outweighing the benefits of increased capacity, due to the need for extensive coordination between threads and resources, which can lead to decreased efficiency and increased strain on computer systems.

Innovation Solution

A core-oriented system control area (COSCA) is introduced, allowing for efficient management of multiple threads by enabling each core to operate in either single-thread or multithreading mode, with a common area representing all cores and separate core description areas for each core, facilitating thread management and reducing hypervisor management overhead through a core dispatch instruction and thread-validity mask.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multithreading is implemented to increase processor capacity, then the number of threads that can operate in parallel increases, but the management overhead increases substantially

Engineering Contradiction:
Improveprocessor capacityVSAvoidmanagement overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system control area is segmented into a common area representing all cores and separate core description areas for each core, with each core description area containing thread description areas. This hierarchical segmentation allows the hypervisor to manage threads at the core level rather than individually, reducing management overhead while maintaining the ability to handle multiple threads in parallel

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a core dispatch instruction as an intermediary mechanism that enables the hypervisor to efficiently manage and dispatch threads to cores. This intermediary instruction simplifies the coordination between the hypervisor and multiple threads, reducing the complexity of direct thread management

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the number of threads is increased to utilize core resources during latency periods, then resource utilization improves, but coordination cost between threads increases

Engineering Contradiction:
Improveresource utilizationVSAvoidcoordination cost
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Multiple threads within a core are merged under a single core description area in the system control area. This merging allows the hypervisor to manage all threads of a core through a unified interface, reducing the time and coordination effort required to manage each thread separately while still allowing them to utilize core resources during latency periods

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If threads share hardware resources to reduce hardware requirements, then hardware savings are achieved, but interference between threads increases

Engineering Contradiction:
Improvehardware requirementsVSAvoidthread interference
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system provides localized control for each core through separate core description areas, allowing thread management and resource allocation to be tailored to the specific characteristics and needs of each core. This localized quality approach enables the hypervisor to optimize thread scheduling and resource allocation for each core individually, reducing interference between threads while maintaining hardware sharing benefits

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9772867B2Control area for managing multiple threads in a computer
Publication Date: 2017.09.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9772867B2 patent drawing
  • US9772867B2 patent drawing
  • US9772867B2 patent drawing

AI summary

Embodiments relate to a control area for managing multiple threads in a computer. An aspect is a computer system that includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread.