Cost-Based Placement Algorithm for Circuit Overlap Resolution

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Solution Overview

Problem

Existing circuit design placement techniques, such as Breadth-First Search, are limited by order dependence and fail to efficiently remove overlaps, leading to infeasible placements that require detailed refinement.

Innovation Solution

A method that selects candidate mobile nodes based on a cost function, iteratively assigns them to gain regions, and adjusts these regions according to the overlap removal rate, using metrics like net-fanout and timing criticality to achieve a legal placement without overlaps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Breadth-First Search technique is used for detailed placement, then all nodes are systematically explored, but the solution is limited by order dependence and fails to efficiently remove overlaps

Engineering Contradiction:

Improveplacement feasibilityVSAvoidoverlap removal efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent changes the selection parameters for mobile nodes from simple BFS ordering to a cost-based metric that considers overlap severity, node mobility, and gain region characteristics. This parameter change enables the algorithm to prioritize nodes that will most effectively reduce overlaps, thereby improving both placement feasibility and overlap removal efficiency simultaneously

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by continuously evaluating the overlap measure after each node assignment and using this information to dynamically adjust the selection of subsequent mobile nodes. The cost function incorporates real-time overlap information, allowing the algorithm to adapt its strategy based on the current placement state, thus efficiently guiding the search toward a legal placement

Inventive Principle:

Principle #23Feedback

2Ease of operation

If gain region is fixed for each candidate node, then assignment is simplified, but convergence to legal placement is slow

Engineering Contradiction:

Improvenode assignment simplicityVSAvoidconvergence time

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The patent makes the gain region dynamic by adjusting its size and scope based on the current overlap measure and the specific characteristics of the candidate mobile node. When overlaps are severe, the gain region expands to include more potential target sites, facilitating faster convergence. When overlaps are reduced, the gain region contracts, refining the search space. This dynamic adjustment maintains ease of operation while significantly improving convergence speed

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7636876B1Cost-based performance driven legalization technique for placement in logic designs

Publication Date: 2009.12.22 XILINX INC

AI summary

A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.