Cost-Constrained Rebuffering Algorithm for IC Net Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional rebuffering optimizations in electronic design automation (EDA) systems for integrated circuit (IC) design are hindered by slow run-time due to the need for extensive processing resources to evaluate numerous rebuffering solutions, which is exacerbated by the lack of effective cost constraints in generating and evaluating rebuffering candidate solutions.
Innovation Solution
Implementing a method that uses a maximum cost constraint to generate rebuffering candidate solutions in a bottom-up manner from sink to source, where buffer cells are placed at bufferable locations along the route connecting the sink to the source, and only solutions that satisfy the cost constraint are saved and propagated to reduce processing overhead, thereby selecting a suitable rebuffering solution efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional rebuffering optimizations evaluate numerous rebuffering solutions without cost constraints, then design objectives like slew, timing, and power can be optimized, but processing resources and run-time increase significantly
Solution Approach 1:
The patent introduces a maximum cost parameter constraint that limits the total cost (area, power, delay) of rebuffering solutions. By changing the parameter space to include cost-constrained solutions only, the algorithm prunes excessive candidate solutions during generation, reducing processing resources while maintaining optimization quality for slew, timing, and power objectives
Solution Approach 2:
The patent performs preliminary cost calculation and constraint checking during the candidate solution generation phase. By evaluating and filtering solutions based on cost constraints before full optimization evaluation, the system eliminates infeasible solutions early, reducing the computational burden on subsequent optimization steps
2Measurement precision
If extensive processing resources are allocated to evaluate rebuffering solutions, then more thorough optimization is achieved, but run-time increases
Solution Approach 1:
The algorithm changes the search space parameters by incorporating cost constraints that limit the number and complexity of candidate solutions evaluated. This parameter modification allows the system to achieve sufficient optimization thoroughness within reduced time limits by focusing computational resources on feasible, cost-constrained solutions rather than exhaustively evaluating all possible solutions
3Productivity
If cost constraints are applied during rebuffering solution generation, then processing resources are reduced, but the search space for optimal solutions is limited
Solution Approach 1:
The patent modifies the solution generation parameters to include cost constraints, which prunes the search space to focus on feasible solutions. This parameter change improves processing efficiency by avoiding generation of obviously infeasible solutions, while the constraint formulation is designed to preserve adaptability by allowing flexible cost thresholds and multiple cost components (area, power, delay) that can be adjusted based on design requirements
Data Source
AI summary
An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.