Programmable Cost Function Circuit for High-Bandwidth PVT Stability
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Solution Overview
Problem
Designing a cost function circuit for high-speed mixed signal integrated circuits is challenging due to varying power and die size requirements, as well as non-ideal properties like process, voltage, and temperature variations, which affect the performance of mixed signal cost function generator circuits, especially in communication systems with high bandwidth needs.
Innovation Solution
A cost function generator circuit is developed with memory terms that include programmable delay elements, analog multipliers, filters to attenuate DC offsets and high-frequency components, digital-to-analog converters, and individually programmable gain analog multipliers to generate inphase and quadrature output currents, which are then transformed into voltage signals using transimpedance amplifiers, addressing variations in process, voltage, and temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog cost function circuit is used to provide polynomial function in high bandwidth applications, then the bandwidth requirement can be met, but the circuit becomes sensitive to PVT variations and other non-ideal properties
Solution Approach 1:
The patent combines digital and analog domains by using digital-to-analog converters (DACs) to generate coefficients that are then used in analog multipliers. This hybrid approach allows the circuit to operate at high bandwidths in the analog domain while using the precision and programmability of the digital domain to compensate for PVT variations through coefficient adjustment.
Solution Approach 2:
The patent employs programmable delay elements and digitally controlled coefficients that can be adjusted to compensate for PVT variations. By changing the delay parameters and coefficient values digitally, the circuit maintains accurate polynomial function generation despite analog component drift due to temperature, voltage, or process variations.
2Reliability
If additional gain stages are added to compensate for PVT variations, then the performance can be improved, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent replaces traditional analog gain stages with digitally controlled coefficient generation. Instead of using additional analog amplification stages to compensate for variations, the system uses digitally programmable coefficients fed through DACs to the analog multipliers, achieving compensation without the power penalty of extra analog gain stages.
Solution Approach 2:
The programmable delay elements and digitally controlled coefficients serve multiple functions: they establish the polynomial function order, compensate for PVT variations, and control the timing of signal processing. This multi-functionality eliminates the need for separate compensation circuits, reducing overall power consumption.
3Reliability
If the polynomial function order is increased to improve signal processing capability, then the performance is enhanced, but the die size and circuit complexity increase
Solution Approach 1:
The patent uses programmable delay elements that can be dynamically configured to implement different polynomial orders. Rather than hardwiring multiple fixed-order polynomial generators, the system can programmatically adjust delay values to achieve the desired function order, reducing the need for multiple dedicated circuit paths and thereby reducing die size.
4Adaptability or versatility
If programmable delay elements and multiple analog multipliers are used to implement high-order polynomial functions, then the signal processing capability is improved, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent employs a universal architecture where programmable delay elements and analog multipliers with digitally controlled coefficients can implement any polynomial order by reconfiguring the delay values and coefficient magnitudes. This single reconfigurable structure replaces what would otherwise require multiple dedicated circuits for different polynomial orders, reducing overall complexity.
Data Source
AI summary
A cost function generator circuit includes memory terms each receiving one or more input signals, and each providing inphase and quadrature output current signals. The inphase and quadrature output currents of the memory terms are summed to provide combined inphase and quadrature output currents, respectively. Transimpedance amplifiers are provided to transform the combined inphase and quadrature output currents into an inphase output voltage and a quadrature output voltage.