Image Sensor Count Circuit With Split Bit Storage for Lower Power
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Solution Overview
Problem
The operation speed and power consumption of count circuits in image sensors are critical factors affecting overall performance, particularly as the number of count circuits increases with image sensor resolution, and existing technologies do not efficiently manage power consumption and peak operation demands.
Innovation Solution
A count circuit design that includes a count block generating count code signals for a predetermined period, with a storage block optimizing power consumption by separating bit signals into high-frequency lower bits and low-frequency upper bits, using distinct control signals for different storage periods to minimize peak and average power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of count circuits is increased to support higher image sensor resolution, then the measurement precision and functionality are improved, but the power consumption increases
Solution Approach 1:
The patent divides the count circuit into multiple independent count blocks, each handling a portion of the pixel array. This segmentation allows power management at the block level, enabling the system to activate only the necessary count blocks based on the active region of the image sensor, thereby reducing overall power consumption while maintaining high resolution capability.
Solution Approach 2:
The patent implements different storage periods for different bit signals within the count circuit. Lower bit signals (which change more frequently) are stored for shorter periods while upper bit signals are stored for longer periods. This local differentiation of storage duration optimizes power consumption by minimizing the active time of storage elements without compromising the ability to capture high-resolution image data.
2Productivity
If the operation speed of count circuit is increased to improve processing performance, then the productivity is improved, but the peak power consumption increases
Solution Approach 1:
The patent employs periodic clock signals with different frequencies for different count blocks and different bit signals. By assigning appropriate clock frequencies based on the requirements of each count block and bit significance, the system achieves high processing speed when needed while allowing lower-speed operation during steady states, thereby reducing peak power consumption while maintaining overall productivity.
Solution Approach 2:
The patent dynamically adjusts the operation speed of different count blocks and storage elements based on the current processing requirements. The controller can selectively enable or disable clock signals to different count blocks and adjust storage periods dynamically, allowing the system to operate at high speed during critical processing phases and at lower speed during stable periods, optimizing the balance between productivity and peak power consumption.
3Reliability
If the storage period for all bit signals is extended to ensure data accuracy, then the reliability is improved, but the average power consumption increases
Solution Approach 1:
The patent segments the storage function into different storage periods for different bit signals. Lower bit signals (which are more prone to noise and change more frequently) are stored for longer periods to ensure accuracy, while upper bit signals are stored for shorter periods. This segmented approach ensures data reliability for critical signals while minimizing the average power consumption by reducing the storage duration for less critical signals.
Solution Approach 2:
The patent applies different storage durations (local quality) to different bit signals based on their significance and noise characteristics. By providing extended storage periods only where necessary for data accuracy while using shorter storage periods elsewhere, the system maintains overall reliability while significantly reducing average power consumption compared to a uniform long storage period approach.
Data Source
AI summary
A count circuit includes a count block suitable for generating count code signals for a predetermined count period including a first period and a second period; and a storage block suitable for storing first bit signals among a plurality of bit signals included in the count code signals, for the first period, and storing remaining bit signals among the plurality of bit signals for the second period.