Counter-Based ADC Architecture for High-Speed Low-Area Conversion
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Solution Overview
Problem
The increasing demand for high-speed operation of multiple analog-to-digital converters (ADCs) in image processing devices leads to significant area and power consumption challenges.
Innovation Solution
The proposed solution includes a comparator, counter, register, and control circuit with a blocking capacitor, along with a reference voltage generator and control circuit, to reduce area and power consumption by optimizing the ADC architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of ADCs are used to process increased data volume, then data processing capability is improved, but area increases significantly
Solution Approach 1:
The ADC is divided into multiple independent conversion circuits that can process different data channels simultaneously. Each conversion circuit handles a portion of the total data load, enabling parallel processing without requiring a single large ADC, thus improving data processing capability while controlling area usage.
Solution Approach 2:
The ADC architecture uses shared components such as a common reference voltage generator and blocking capacitors that serve multiple conversion circuits. This multi-functionality allows the same hardware resources to be utilized across multiple data processing channels, improving overall productivity without proportionally increasing area.
2Productivity
If ADCs operate at high operating speed to handle large data volumes, then data processing capability is improved, but power consumption increases
Solution Approach 1:
The ADC employs periodic sampling and conversion cycles where conversion circuits are activated in alternating time periods. This periodic operation allows high-speed processing capability while reducing average power consumption by keeping circuits in low-power states between active conversion periods.
Solution Approach 2:
Multiple conversion circuits share common power supply networks, reference voltage generation, and control logic. By merging these resources, the total power consumption is reduced compared to having completely independent high-speed ADCs, while still maintaining the ability to process large data volumes through parallel operation.
3Productivity
If multiple ADCs are deployed to process increased data volume, then data processing capability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple conversion circuits into a single ADC device with shared resources including reference voltage generator, blocking capacitors, and control logic. This consolidation allows the system to process increased data volumes through parallel conversion circuits while avoiding the proportional power consumption increase that would result from completely separate ADC devices.
Solution Approach 2:
Shared components such as the reference voltage generator and blocking capacitors serve multiple conversion circuits simultaneously. This multi-functionality enables the system to achieve high data processing capability through parallel processing while reducing total power consumption by eliminating redundant components in each individual ADC.
Data Source
AI summary
An ADC device includes: a comparator having first and second input terminals and an output terminal and being configured to compare an input signal input through the first input terminal with a reference voltage input through the second input terminal to output a comparison result value through the output terminal, the reference voltage being decreased by a preset value from a previous value in response to a clock signal; a counter configured to output a digital count value that increases each time the clock signal toggles; a register configured to latch the digital count value based on the comparison result value and generate a digital value corresponding to the input signal based on the latched digital count value; a blocking capacitor connected to the first input terminal and configured to transmit the input signal to the first input terminal; and a control circuit configured to generate the clock signal.