Counter Array Segmentation for High-Frequency Overflow Handling
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Solution Overview
Problem
High-frequency counter arrays face resource constraints due to the disconnect between counter update frequency and hardware operation rate, leading to increased costs, power requirements, and routing complexity.
Innovation Solution
Organizing statistics circuits with a main block of counters operating at a frequency greater than or equal to half the counter update frequency, and a cache counter block to handle overflows, ensuring only one block overflows simultaneously, thereby reducing resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If counters are updated at high frequency to monitor packet connections, then monitoring accuracy is improved, but device size and power requirements increase
Solution Approach 1:
The patent divides the counter array into multiple blocks, where each block can be independently updated at a lower frequency. This segmentation allows the system to maintain high-frequency monitoring capability through selective updating while reducing the overall resource requirements compared to updating all counters at maximum frequency.
2Measurement precision
If counters are updated at high frequency, then monitoring accuracy is improved, but power consumption increases
Solution Approach 1:
By segmenting the counter array into blocks that can be independently controlled, the system updates only necessary blocks at high frequency while updating other blocks at lower frequencies or not at all, thereby maintaining monitoring accuracy for critical counters while significantly reducing overall power consumption.
3Adaptability or versatility
If more counters are implemented to handle high update rates, then monitoring capability is improved, but routing complexity increases
Solution Approach 1:
The counter array is organized into multiple manageable blocks with standardized interfaces. This segmentation simplifies the routing architecture by allowing regular patterns in data flow and control signals, reducing the complexity that would otherwise arise from handling individual high-frequency counter updates.
Solution Approach 2:
The patent implements a universal counter block design that can be replicated and configured for different monitoring needs. This multi-functionality allows the same hardware structure to serve multiple purposes, reducing overall routing complexity compared to implementing specialized counters for each function.
Data Source
AI summary
Systems and method include receiving counter update requests that are at a maximum frequency of fcounters; sending the counter update requests to a main block of counters that operate at a maximum frequency of fmain, where (fmain)≥(fcounters)/2; and responsive to a block of the main block of counters experiencing an overflow, sending corresponding counter update requests for the block of the main block of counters experiencing the overflow to a cache counter block that operates at a maximum frequency of fcache, where (fmain)≥(fcache) and (fcache)≥(fcounters)−(fmain). The counter update requests can be for Y×K total counters, and the main block of counters can include Y blocks of counters each block having K counters, Y and K are positive integers. (fmain)≥(fcounters)/2 ensures only one block of the main block of counters overflows simultaneously.