Counter-Based SYSREF Synchronization for Cascaded Clock Dividers
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Solution Overview
Problem
As device input clock frequencies increase, ensuring proper setup and hold margins for the latched SYSREF pulse across variations in process, voltage, and temperature becomes challenging, especially when the SYSREF and device clock are asynchronous, leading to uncertainty in the periodicity of the latched SYSREF pulse with respect to the device clock in cascaded clock divider systems.
Innovation Solution
A system comprising an input flip-flop, a counter, and cascaded clock dividers, where the counter counts device clock pulses initiated by the latched SYSREF signal to generate an internally periodic SYSREF signal, eliminating the need for external SYSREF pulses and reducing coupling by gating off the counter's output after synchronization, ensuring all clock dividers remain synchronized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device input clock frequency is increased, then the productivity and performance of the system is improved, but it becomes difficult to guarantee proper setup and hold margins at the flip-flop that latches SYSREF across variations in process, voltage, and temperature
Solution Approach 1:
The patent applies preliminary action by generating the SYSREF signal internally before it is needed by the clock dividers. The SYSREF signal is generated at a divided-down frequency that ensures proper timing margins are met, and this pre-generated signal is then used to synchronize all clock dividers in the cascaded structure, eliminating the timing margin problems associated with high-frequency external SYSREF signals
Solution Approach 2:
The patent changes the frequency parameter of the SYSREF signal by dividing it down using a clock divider before distributing it to the clock divider chain. This parameter transformation from high frequency to divided-down frequency resolves the setup and hold margin issues while maintaining synchronization across all clocks in the system
2Adaptability or versatility
If the SYSREF and device clock input to the chip are asynchronous, then the system has more flexibility in clock source selection, but the periodicity of the latched SYSREF pulse cannot be guaranteed with respect to device clock
Solution Approach 1:
The patent introduces an intermediary clock divider that receives both the external SYSREF signal and the device clock, and generates a new SYSREF signal that is inherently synchronized to the device clock. This intermediary component mediates between the asynchronous inputs and the clock divider chain, ensuring periodicity is guaranteed with respect to the device clock while still allowing flexible clock source selection
Solution Approach 2:
The patent replaces the mechanical/latched approach to SYSREF synchronization with a systematic clock division approach. Instead of relying on flip-flop latching of asynchronous SYSREF signals, the system uses a clock divider to generate SYSREF pulses that are mathematically guaranteed to be periodic with the device clock, providing deterministic synchronization
3Reliability
If external SYSREF pulses are continuously used to synchronize cascaded clock dividers, then all clock dividers remain synchronized, but power consumption and heat generation increase
Solution Approach 1:
The patent implements self-service by enabling the clock dividers to generate their own synchronization signal internally. The first clock divider generates the SYSREF signal from the device clock, and this internally-generated signal is then distributed to synchronize the remaining clock dividers in the cascade, eliminating the need for continuous external SYSREF pulses and reducing power consumption
Solution Approach 2:
The patent extracts the SYSREF signal generation function from the external domain and places it within the chip's internal clock tree. By taking out the dependency on external SYSREF pulses and generating the signal internally using the device clock as the source, the system maintains synchronization reliability while eliminating the power and heat issues associated with continuous external signal distribution
Data Source
AI summary
A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.