Digital Counter Bit-Transition Testing for Fast Boot Verification
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Solution Overview
Problem
Existing methods for testing counters in safety-critical systems, such as Software Watchdog Timers, are time-intensive and unsuitable for high-resolution counters, exceeding the required boot time of 50 milliseconds.
Innovation Solution
A method for testing digital hardware counters using a software module that sequentially checks the most significant bits of the count value by enabling and disabling the counter, verifying bit transitions and final values, allowing for efficient testing of counters with 16, 32, or 64 bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional counter testing methods are used to ensure thorough verification, then testing completeness is improved, but boot time exceeds the required 50 milliseconds
Solution Approach 1:
The patent segments the counter testing process into distinct phases: initialization phase, counting phase, and verification phase. By dividing the testing into discrete steps with specific control points, the system can efficiently verify counter functionality without requiring exhaustive testing of all possible count values, thus reducing overall test time while maintaining reliability
Solution Approach 2:
The patent implements preliminary actions by pre-configuring test parameters, initializing counter values, and preparing verification criteria before the actual counting operation begins. This allows the testing process to start immediately with predefined conditions, eliminating setup delays during the critical boot sequence
2Measurement precision
If high-resolution counters with 16, 32, or 64 bits are tested using conventional methods, then measurement precision is improved, but testing duration becomes excessively long
Solution Approach 1:
The patent uses a software module as a virtual controller that mimics the behavior of the hardware counter. This software copy can be configured to match any resolution (16, 32, or 64 bits) and can be tested instantaneously through software logic rather than physically counting through all values, dramatically reducing testing duration while preserving measurement precision verification
Solution Approach 2:
The patent changes the testing parameter from actual count value verification to control signal verification. Instead of testing by counting through all possible values (which would take exponentially longer with increased resolution), the system tests by verifying that the counter responds correctly to control signals (start, stop, reset) across different resolution configurations
Data Source
AI summary
Solutions for testing a digital hardware counter circuit are disclosed. In an example, a software module tests a plurality of most significant bits. The count value is set to a binary value. For a down counter, the bit of the binary value at the current bit position is set to high and lower bits are set to low. For an up counter, the bit of the binary value at the current bit position is set to low and lower bits are set to high. Next, the software module enables the counter. The counter varies the count value. After a time-period, the software module disables the counter and determines whether one or more bits of the count value have an expected value(s). When at least one of the one or more bits of the count value does not have the respective expected value, the software module signals a malfunction.