On-Chip Initialization Counter Circuit BIST Testing
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Solution Overview
Problem
There is a need for an efficient and automated testing procedure for on-chip initialization circuits in integrated circuits, particularly for the crystal "warm up" delay counter, which current methods do not adequately address, requiring additional circuitry and being time-consuming.
Innovation Solution
A Built-In Self Test (BIST) module with a state machine and counter is introduced, capable of testing the initialization counter circuit by splitting it into sub-counters and verifying states through specific signal configurations and timing diagrams, allowing for efficient testing without increasing the operating speed of the crystal oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the initialization counter circuit is tested by traversing all 2^24 states, then complete verification is achieved, but test time becomes excessively long (0.32 seconds at 50 MHz)
Solution Approach 1:
The 24-bit counter is divided into two 12-bit sub-counters, reducing the test space from 2^24 states to 2^13 states. This segmentation allows the test to verify critical functionality while reducing test time from 0.32 seconds to 160 microseconds, achieving a balance between verification completeness and time efficiency.
2Loss of time
If additional circuitry is added to facilitate accelerated testing, then test time is reduced, but device complexity increases
Solution Approach 1:
The initialization counter circuit performs self-testing by utilizing its own internal structure. The test mechanism uses the counter's existing flip-flop circuits and clock signals to verify its operation, eliminating the need for external test circuitry. This self-service approach reduces device complexity while achieving accelerated testing.
3Reliability
If the counter tests all states sequentially, then complete state verification is achieved, but testing efficiency decreases
Solution Approach 1:
By segmenting the counter into two 12-bit sub-counters, the test only needs to traverse 2^13 states instead of 2^24 states. This reduces the testing workload by a factor of 2000, improving productivity from testing all states sequentially to testing only critical transition states, while maintaining verification reliability through targeted state checking.
Data Source
AI summary
An apparatus and method is disclosed for providing automated testing for an on-chip initialization counter circuit that comprises a plurality of counter flip-flop circuits that are used in the initialization of an integrated circuit. The apparatus comprises a state machine and a state machine counter circuit. The state machine receives signals from the initialization counter circuit and utilizes the signals to create a built-in self test output signal that indicates a current state within the initialization counter circuit. The state machine is capable of testing various operational states of an initialization counter circuit.