Counter-Based Clock Domain Generation for Microprocessor Synchronization

Solution Overview

Problem

High frequency clock signal paths in microprocessors are costly and complex, consuming significant chip area and power, while maintaining synchronization between components is crucial for proper operation.

Innovation Solution

Implementing a microprocessor design with counter devices that generate synchronized and ratioed clock signals within logic domains, reducing the need for high frequency signal paths and using synchronization pulse signals for communication between domains, and employing a low frequency reset signal to synchronize counters without additional high frequency paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high frequency clock signal paths are implemented throughout the microprocessor chip, then synchronization between components is maintained, but chip area consumption and power usage increase significantly

Engineering Contradiction:

Improvesynchronization between componentsVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The microprocessor chip is divided into multiple logic domains, each with its own local counter device that generates clock signals independently. This segmentation eliminates the need for extensive high-frequency clock signal distribution paths across the entire chip, as each domain generates its own synchronized clocks locally from a single shared high-frequency clock input.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Counter devices serve as intermediary components that convert a single shared high-frequency clock signal into multiple domain-specific clock signals. These counters act as local clock generators that maintain synchronization with the master clock without requiring direct high-frequency signal paths from the clock source to each logic domain.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If high frequency clock signal paths are implemented throughout the microprocessor chip, then synchronization between components is maintained, but power consumption increases

Engineering Contradiction:

Improvesynchronization between componentsVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The microprocessor chip is divided into multiple logic domains, each with its own local counter device that generates clock signals independently. This segmentation eliminates the need for extensive high-frequency clock signal distribution paths across the entire chip, as each domain generates its own synchronized clocks locally from a single shared high-frequency clock input.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Counter devices serve as intermediary components that convert a single shared high-frequency clock signal into multiple domain-specific clock signals. These counters act as local clock generators that maintain synchronization with the master clock without requiring direct high-frequency signal paths from the clock source to each logic domain.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of operation

If high frequency clock signal paths are implemented throughout the microprocessor chip, then clock distribution is achieved, but design complexity increases

Engineering Contradiction:

Improveclock distributionVSAvoiddesign complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The microprocessor chip is divided into multiple logic domains, each with its own local counter device that generates clock signals independently. This segmentation eliminates the need for extensive high-frequency clock signal distribution paths across the entire chip, as each domain generates its own synchronized clocks locally from a single shared high-frequency clock input.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Counter devices serve as intermediary components that convert a single shared high-frequency clock signal into multiple domain-specific clock signals. These counters act as local clock generators that maintain synchronization with the master clock without requiring direct high-frequency signal paths from the clock source to each logic domain.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9218018B2Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain

Publication Date: 2015.12.22 ORACLE INT CORP

AI summary

Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals within a processing device. In particular, one or more counter devices may be integrated into a microprocessor design that operates on a system clock signal to provide ratioed synchronous clock signals for use by the microprocessor. Additionally, one or more synchronization pulse signals are also generated from the one or more counter devices to facilitate communication between domains of the microprocessor that may operate on separate clock frequencies. Such synchronization pulse signals may also provide for a virtual clock signal within a clock domain to create a low frequency logic cluster within a high frequency domain of the microprocessor. A synchronous, low frequency reset signal is also disclosed to synchronize the counting devices to the system clock without the need for an additional high frequency signal path in the microprocessor design.