Counter-Comparator Frequency Multiplication for Accurate Fundamental Sensing

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Solution Overview

Problem

Existing frequency multiplication techniques are inadequate for precise and cost-effective measurement of fundamental frequencies, particularly in applications requiring high multiplication factors, leading to inaccuracies and complexities in spectral analysis and power grid measurements.

Innovation Solution

A frequency multiplying device that generates a reference signal with a frequency f osc and a further reference signal with frequency f K, allowing for high-accuracy frequency multiplication without knowing the individual frequencies, using a simple hardware structure with counters and a comparator to achieve a multiplication factor arbitrarily high, up to 10^5, and suitable for compact, low-cost devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional frequency multiplication techniques are used, then frequency multiplication can be achieved, but measurement precision and reliability deteriorate due to spectrum leakage and aliasing effects

Engineering Contradiction:
Improvefrequency measurement precisionVSAvoidmeasurement reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by performing frequency multiplication before the measurement process. The counter circuit multiplies the input frequency by a predetermined factor N to generate a multiplied frequency signal, which is then used for subsequent spectral analysis. This preliminary frequency multiplication ensures that the measurement is performed at a higher frequency where spectrum leakage and aliasing effects are minimized, thereby improving both measurement precision and reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through a phase-locked loop (PLL) circuit that continuously monitors the multiplied frequency signal and adjusts the counter circuit to maintain accurate frequency multiplication. The PLL compares the phase of the input signal with the multiplied signal and generates a feedback control signal to correct any frequency deviations, ensuring reliable and precise frequency measurements even in the presence of signal variations

Inventive Principle:
Principle #23Feedback

2Measurement precision

If high multiplication factors are used to overcome spectrum leakage, then measurement accuracy improves, but device complexity increases

Engineering Contradiction:
Improvespectral measurement accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical or analog frequency multiplication circuits with a digital counter-based system. Instead of using traditional analog multipliers or phase modulators, the invention uses a simple counter circuit that counts input clock cycles and generates output pulses at a predetermined multiplication factor N. This digital approach significantly reduces circuit complexity while maintaining high multiplication factors necessary for accurate spectral measurements

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent achieves high multiplication factors by changing the counting parameter N in the counter circuit. By simply adjusting the predetermined count value N, the system can achieve different multiplication factors (e.g., 10x, 100x, 1000x) without any hardware changes. This parameter-based approach allows flexible adjustment of multiplication factor to match measurement requirements while keeping the device structure simple and uncomplicated

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If numerical post-processing is used to compensate frequency errors, then some accuracy can be recovered, but loss of time occurs due to additional processing steps

Engineering Contradiction:
Improvefrequency accuracyVSAvoidmeasurement time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent eliminates the need for time-consuming post-processing by performing frequency multiplication in advance, before the measurement is taken. The counter circuit pre-multiplies the input frequency by factor N, and the measurement is then performed directly on the multiplied signal. This preliminary action ensures that the measurement is completed in a single step without requiring additional computational processing, thereby recovering frequency accuracy while avoiding time loss

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the frequency multiplication function from the measurement process itself and performs it separately in advance. By separating the frequency multiplication step from the measurement step, the system can prepare the multiplied frequency signal beforehand, and then perform the actual measurement quickly without needing to perform complex numerical post-processing to correct frequency errors, thus reducing overall measurement time while maintaining precision

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP3405797B1Frequency multiplying device
Publication Date: 2019.12.11 SMART GRID SOLUTIONS GMBH
  • EP3405797B1 patent drawingFigure 1
  • EP3405797B1 patent drawingFigure 2
  • EP3405797B1 patent drawingFigure 3

AI summary

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f0Sc, wherein fosc is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.