Counter-doped Three-Region Gate Reduces GIDL
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Solution Overview
Problem
As integrated circuit devices shrink, they face challenges such as increased gate-induced drain leakage (GIDL), which raises power consumption and heat generation, and existing solutions like increasing gate oxide thickness or using an extended drain degrade device performance by increasing area requirements.
Innovation Solution
A three-region counter-doped conductive gate structure is introduced, comprising a first and second gate region of a second conductivity type and a third gate region of the first conductivity type, which increases the polysilicon work function and threshold voltage, reducing GIDL without adding new processing steps by modifying the poly pre-dope implant mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are reduced to improve integration density, then productivity increases, but gate induced drain leakage increases causing higher power consumption
Solution Approach 1:
The gate electrode is segmented into three distinct regions with different conductivity types: a first gate region with first conductivity type, a second gate region with second conductivity type, and a third gate region with first conductivity type. This segmentation allows each region to perform different functions in controlling the channel, reducing GIDL while maintaining effective channel control with the reduced gate oxide thickness.
Solution Approach 2:
Different regions of the gate electrode are doped with different conductivity types to create localized functional zones. The first and third gate regions with first conductivity type control leakage at their respective interfaces, while the second gate region with second conductivity type controls the central channel portion, optimizing performance locally throughout the gate structure.
2Use of energy by moving object
If gate oxide thickness is increased to reduce GIDL, then power consumption decreases, but device area increases
Solution Approach 1:
The gate electrode is divided into three doped regions with alternating conductivity types, allowing the gate oxide thickness to be reduced while compensating for leakage effects through the specific doping configuration. This enables maintaining thin gate oxide for compact devices while controlling GIDL through the segmented doping structure.
Solution Approach 2:
The conductivity type parameter is changed along the gate electrode length, creating regions of alternating conductivity types. This parameter variation allows the gate to effectively control channel leakage without requiring increased gate oxide thickness, thus maintaining compact device area while reducing power consumption.
3Use of energy by moving object
If extended drain is used to reduce GIDL, then power consumption decreases, but device area increases
Solution Approach 1:
Instead of extending the drain region laterally (which increases area), the gate electrode is segmented into three vertical regions with different conductivity types. This vertical segmentation approach reduces GIDL through controlled doping profiles without requiring additional lateral space, maintaining compact device area while reducing power consumption.
Solution Approach 2:
The solution transitions from a lateral extension approach (extended drain in the horizontal plane) to a vertical segmentation approach (three-region gate structure in the vertical dimension). By solving the GIDL problem in the vertical dimension through alternating conductivity regions rather than lateral extension, device area is maintained while power consumption is reduced.
4Use of energy by moving object
If three-region counter-doped gate structure is implemented to reduce GIDL, then power consumption decreases, but device complexity increases
Solution Approach 1:
The three-region gate structure is formed by combining the gate electrode with alternating doping regions integrated into a single continuous structure. This merging approach allows the complex three-region functionality to be achieved without separate discrete components, reducing fabrication complexity while maintaining the power consumption benefits.
Solution Approach 2:
The segmented gate structure serves multiple functions simultaneously: it controls the channel, reduces GIDL at both drain interfaces, and maintains effective electric field control with thin gate oxide. This multi-functionality is achieved within a single integrated gate structure rather than requiring separate components, balancing functionality with structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-region conductive gate structure decreases GIDL, allows for reduced channel doping, and provides a buffer for high voltage implants, thereby improving device performance and reducing power consumption without increasing device area.
Implementation Method 1
The third gate region extends between the first gate region and the second gate region and is of the first conductivity type. The three-region structure of the conductive gate increases the polysilicon work function at the center region of the MOS transistor, increasing the threshold voltage of the MOS transistor by up to 1 volt or more.
Implementation Method 2
The three-region structure of the conductive gate increases the polysilicon work function at the center region of the MOS transistor, increasing the threshold voltage of the MOS transistor by up to 1 volt or more. This permits channel doping to be decreased and reduces gate induced drain leakage.
Implementation Method 3
The three-region structure of the conductive gate also provides a buffer for penetration of a high voltage, lightly doped drain implant through a poly gate of the integrated circuit device and into a channel of the integrated circuit device during fabrication of the integrated circuit device.
Data Source
AI summary
Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.