Counter-Gated Clock Division for Low-Skew Non-Integer Sub-Clocks
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Solution Overview
Problem
Existing clock generation systems introduce skew and are complex, limiting their ability to efficiently generate low power designs with sub clock divisions and non-integer clock waves.
Innovation Solution
A combined positive and negative clock gate circuit using AND gates, transparent low latches, and digital comparators to enable low-skew clock division by integer and non-integer factors, allowing for flexible and scalable clock generation with phase shifting capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascade of flip flops is used to generate low order divided clocks, then clock division is achieved, but skew is introduced and device complexity increases
Solution Approach 1:
The patent replaces the mechanical/cascaded flip-flop system with a fully digital counter-based system. The counter circuit counts clock cycles and generates enable signals for clock gates, eliminating the need for cascaded flip-flops and their associated skew. This substitution of the clock division mechanism with a digital counting approach resolves the contradiction by removing the source of skew while simplifying the overall device structure.
Solution Approach 2:
The patent segments the clock division function into independent clock gates, each controlled by its own counter and comparator. Instead of a single cascaded system, multiple independent clock division channels are created, each handling specific division ratios. This segmentation eliminates the cumulative skew that occurs in cascaded systems while maintaining the ability to generate multiple divided clock signals.
2Adaptability or versatility
If complicated selection mechanisms are used for clock generation, then clock division is achieved, but device complexity increases
Solution Approach 1:
The patent implements a universal clock division architecture where a single counter circuit can generate enable signals for multiple clock gates with different division ratios. By programming the counter modulus and comparator values, the same hardware structure can accommodate various clock division requirements (integer and non-integer ratios), eliminating the need for separate dedicated circuits for each division ratio and simplifying the overall device complexity.
3Adaptability or versatility
If traditional clock generation methods are used, then integer clock division is achieved, but non-integer clock waves cannot be generated
Solution Approach 1:
The patent introduces dynamic control of clock gate enable signals through programmable counters and comparators. The counter modulus and comparator threshold values can be dynamically adjusted to generate both integer and non-integer clock division ratios. This dynamic configurability allows the system to adapt to different clock division requirements while maintaining accurate timing through the synchronous counter-based approach, resolving the contradiction between versatility and accuracy.
Data Source
AI summary
The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free.