Synchronized Counter-Group ADC for High-Speed Image Sensors
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Solution Overview
Problem
In semiconductor integrated circuits, particularly in analog-to-digital converters and image sensors, the increasing number of counters and operational frequency lead to mismatches due to propagation delays of clock signals, degrading the performance and increasing power consumption.
Innovation Solution
The implementation of a pixel array with grouped counters and synchronization circuits that synchronize input clock signals using a source clock signal with phase differences, allowing counters to operate at a lower frequency and reducing power consumption while maintaining high counting speed through phase-division schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of counters is increased to handle higher resolution image signals, then the conversion capability is improved, but the propagation delay mismatches worsen and power consumption increases
Solution Approach 1:
The patent divides the large number of counters into multiple counter groups, with each group receiving synchronized clock signals from dedicated synchronization circuits. This segmentation allows each group to operate with precise clock synchronization while collectively handling high-resolution image signals, thus improving conversion capability without worsening synchronization reliability.
Solution Approach 2:
The patent introduces synchronization circuits as intermediary components between the clock signal source and the counter groups. These synchronization circuits generate synchronized input clock signals for each counter group, acting as mediators that eliminate propagation delay mismatches and ensure reliable clock synchronization across all counters handling high-resolution signals.
2Productivity
If the operational frequency is increased to improve imaging speed, then the productivity is improved, but the propagation delay mismatches worsen
Solution Approach 1:
The patent implements preliminary synchronization of clock signals before they are distributed to counter groups. The synchronization circuits pre-adjust the clock signals to ensure they are properly synchronized at high frequencies, preventing propagation delay mismatches from occurring in the first place and enabling high-speed imaging operation.
Solution Approach 2:
The patent changes the frequency parameter of the source clock signal to be higher than the input clock signal frequency. This parameter change allows the synchronization circuits to generate multiple synchronized input clock signals at the required operational frequency, improving imaging speed while maintaining reliable clock signal matching through the synchronization mechanism.
3Quantity of substance
If the number of counters is increased to handle more pixels, then the processing capability is improved, but the power consumption increases
Solution Approach 1:
The patent segments the large number of counters into multiple counter groups that operate with synchronized clock signals. This segmentation enables efficient batch processing of pixel signals, allowing the system to handle a large quantity of pixels through coordinated counter groups rather than independently operating counters, thereby reducing overall power consumption.
Solution Approach 2:
The patent ensures continuous operation of counter groups with synchronized clock signals, allowing seamless processing of pixel data streams. This continuous operation eliminates idle states and reconfiguration overhead, enabling the system to maintain high processing capability for large numbers of pixels while optimizing power consumption through efficient resource utilization.
Data Source
AI summary
An image sensor includes a pixel array, a plurality of comparators, a plurality of counters and a plurality of synchronization circuits. The pixel array includes a plurality of pixels configured to generate analog signals by sensing incident light. The comparators generate comparison signals by comparing the analog signals with a reference signal. The counters are grouped into a plurality of counter groups. Each of the counters generates digital signals corresponding to the analog signals by counting, the counting terminated by the comparison signals. Each of the synchronization circuits synchronizes input clock signals to a source clock signal to provide synchronized input clock signals to each of the counter groups.