Formal Verification of Hardware Counters via Inductive Assertions
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Solution Overview
Problem
Existing methods for verifying the operation of large counters in hardware designs, such as system-on-chips, become infeasible due to the vast number of possible combinations, making it difficult to detect bugs using simulation-based or formal verification methods.
Innovation Solution
Formally verifying an inductive assertion that establishes a relationship between the counter and a test bench counter from a non-reset state, allowing the formal verification tool to focus its checking in the vicinity of a bug, thereby efficiently identifying and correcting bugs in large counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive verification through simulation-based verification or formal verification methods is used, then verification completeness is improved, but verification feasibility deteriorates due to the large number of possible combinations in large counters
Solution Approach 1:
The patent divides the verification process into two distinct phases: (1) bug identification phase using inductive assertions to quickly locate potential bugs, and (2) exhaustive verification phase using non-inductive assertions to prove correctness. This segmentation allows each phase to use the most appropriate verification method for its specific goal, avoiding the need to perform exhaustive verification from scratch when bugs are present.
Solution Approach 2:
The patent performs preliminary bug identification using inductive assertions before conducting exhaustive verification. By first using a faster, targeted approach to identify potential bug locations, the system prepares the ground for more efficient exhaustive verification by focusing computational resources on relevant state spaces rather than exploring the entire state space uniformly.
2Reliability
If formal verification is performed from a reset state, then verification thoroughness is improved, but verification time increases significantly for large counters
Solution Approach 1:
The patent segments the verification process into a preliminary phase (bug identification from any state using inductive assertions) and a final phase (exhaustive verification from reset state using non-inductive assertions). This allows the time-consuming exhaustive verification to be performed only after bugs have been identified and eliminated, making the overall process feasible.
Solution Approach 2:
The patent performs preliminary verification using inductive assertions that can start from non-reset states, which is much faster than exhaustive verification from reset. This preliminary action eliminates obvious bugs early, so that subsequent exhaustive verification from reset state operates on a cleaner, bug-free design, reducing overall verification time.
3Reliability
If the entire state space is explored exhaustively, then bug detection capability is improved, but computational resources required deteriorate for large counters
Solution Approach 1:
The patent segments bug detection into two stages: (1) rapid bug identification using inductive assertions that can quickly pinpoint problematic states without exhaustive exploration, and (2) targeted exhaustive verification using non-inductive assertions only after bugs are eliminated. This segmentation dramatically reduces computational resource consumption while maintaining complete bug detection capability.
Solution Approach 2:
The patent introduces inductive assertions as an intermediary mechanism that bridges the gap between fast but incomplete verification and slow but complete verification. Inductive assertions act as a filter that quickly identifies and eliminates obvious bugs, allowing the expensive exhaustive verification to operate more efficiently on refined designs.
Data Source
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AI summary
A method of detecting a bug in a counter of a hardware design that includes formally verifying, using a formal verification tool, an inductive assertion from a non-reset state of the hardware design. The inductive assertion establishes a relationship between the counter and a test bench counter at two or more points in time, !f the formal verification tool identifies at least one valid state of the counter in which the inductive assertion is not true, information is output indicating a location of a bug in the counter or the test bench counter.