Counter Integrity Tree Split-Node Memory Security
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Solution Overview
Problem
Data processing systems face challenges in securing sensitive information stored in external memory, which is vulnerable to attacks, as existing security measures like encryption and integrity checks incur performance costs and may not be feasible due to limited capacity in secure memory.
Innovation Solution
Implementing a counter integrity tree with split-counter nodes that maintain a main counter integrity tree and a mirror counter integrity tree, allowing for efficient verification of data integrity by comparing stored and calculated authentication codes, and dynamically adjusting minor counter sizes based on access patterns to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption and integrity checks are implemented for data stored in external memory, then security against attacks is improved, but performance deteriorates due to additional calculations and memory accesses
Solution Approach 1:
The patent segments the counter integrity tree into multiple levels (root level, intermediate levels, and leaf level), where each level stores counters for different groups of data blocks. This hierarchical segmentation reduces the number of memory accesses required for integrity verification by allowing the system to traverse only the necessary path from leaf to root rather than accessing all counters, thus improving performance while maintaining security.
Solution Approach 2:
The patent pre-calculates and stores authentication codes (integrity metadata) for data blocks when they are written to external memory. These pre-computed authentication codes are stored alongside the data, eliminating the need to perform complex integrity calculations during read operations. This preliminary action significantly reduces the computational overhead during data access while maintaining robust integrity verification.
2Reliability
If all sensitive information is stored in secure on-chip memory, then security is improved, but storage capacity deteriorates due to limited on-chip memory
Solution Approach 1:
The patent introduces an integrity tree data structure as an intermediary between secure on-chip memory and insecure external memory. The root and intermediate level counters of the integrity tree are stored in secure on-chip memory, while the leaf level counters and actual data blocks are stored in external memory. This intermediary structure allows the system to leverage limited secure memory capacity while providing security guarantees for data in external memory through cryptographic authentication.
3Reliability
If the counter integrity tree is traversed to verify data integrity, then security is improved, but the number of memory accesses increases
Solution Approach 1:
The counter integrity tree is segmented into levels where the root level contains a single counter, intermediate levels contain counters for groups of data blocks, and the leaf level contains counters for individual data blocks. During integrity verification, the system only needs to traverse the specific path from the leaf node to the root node, accessing a logarithmic number of counters rather than all counters in the tree. This segmentation dramatically reduces memory access time while maintaining complete integrity verification.
Data Source
AI summary
A counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree.


