Counter Interface Circuit for Solid-State Imaging Data Latch Multiplexing
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Solution Overview
Problem
In solid-state imaging devices, the existing methods for transferring analog pixel signals from column cores to a logic circuit are inefficient, requiring additional memory for signal rearrangement and leading to increased power consumption and decreased output rates during thinning or partial column readouts.
Innovation Solution
A solid-state imaging device configuration that includes data latches connected to a counter interface circuit, which outputs data in units of predetermined channels, and a logic circuit for digital conversion, utilizing multiple-stage selector groups and a shift register to manage the HSEL pulse and clock signals for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pixel signals are transferred from multiple columns to the logic circuit simultaneously to increase transfer speed, then the data transfer speed is improved, but memory is required for temporary signal storage and rearrangement
Solution Approach 1:
The patent extracts the signal rearrangement function from the logic circuit and implements it in the counter interface circuit instead. This allows the logic circuit to focus solely on digital conversion while the counter interface circuit handles the multiplexing and rearrangement of pixel signals from multiple columns, eliminating the need for additional memory in the logic circuit.
Solution Approach 2:
The counter interface circuit acts as an intermediary between the column cores and the logic circuit. It receives pixel signals from multiple columns, performs the necessary rearrangement and multiplexing, and then outputs the processed signals to the logic circuit for digital conversion, thereby resolving the conflict between fast parallel transfer and memory requirements.
2Reliability
If pixel signals are read from all columns and then extracted for necessary columns, then complete data acquisition is achieved, but power consumption increases and output rate decreases
Solution Approach 1:
The counter interface circuit enables partial readout by allowing selective activation of column cores. Instead of reading from all columns simultaneously, the system can activate only the necessary columns based on the imaging requirements, thereby reducing power consumption while maintaining data acquisition reliability for the required regions.
Solution Approach 2:
The patent implements dynamic column selection capability where the system can adaptively activate or deactivate column cores based on the specific imaging task. This dynamic control allows the system to optimize power consumption by reading only from necessary columns while maintaining the ability to acquire complete data when needed.
3Reliability
If pixel signals are read from all columns and then extracted for necessary columns, then complete data acquisition is achieved, but the output rate decreases
Solution Approach 1:
The counter interface circuit segments the column outputs into multiple groups and processes them in an organized manner. By dividing the column signals into manageable groups and using multiple output channels, the circuit can efficiently rearrange and output pixel signals without bottlenecking the overall data flow, thereby maintaining high output rates even when performing selective column readout.
Solution Approach 2:
The counter interface circuit provides multi-functional capability by supporting both full-column readout and selective column readout operations. It can dynamically configure its internal routing to handle different readout patterns, ensuring high output rates are maintained regardless of whether all columns or only selected columns are being read, thus improving productivity across different operating modes.
Data Source
AI summary
A solid-state imaging device includes: a large number of column cores configured to output analog outputs of pixels disposed vertically and horizontally in a vertical direction; a large number of data latches configured to hold the analog outputs of the large number of column cores, respectively; a counter interface circuit directly connected to the large number of data latches, and configured to output outputs of the large number of data latches in units of a predetermined number of output channels; and a logic circuit configured to perform digital conversion on the outputs of the large number of data latches being input in units of the predetermined number of output channels through the counter interface circuit.