Counter Management Algorithm Memory Segmentation
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Solution Overview
Problem
As data network speeds increase, conventional hardware-based flow statistics collection methods become costly, power-intensive, and area-consuming due to the need for expensive high-speed external memories, which are inefficient in managing counter widths and depths for multi-hundred gigabit systems.
Innovation Solution
The method involves using a combination of high-speed SRAM for caching the highest speed portion of counters and low-speed DRAM for storing the entire counter, leveraging rollover bits to manage data transfer between the two memory types, allowing for faster updates and reducing the need for extensive high-speed memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If very high speed external memories (QDRII SRAM, RLDRAM) are used for flow statistics collection, then counter update speed and width are improved, but cost, power consumption, and area requirements increase significantly
Solution Approach 1:
The patent segments the counter storage system into two parts: high-speed memory for storing only the most significant bits (MSBs) that change slowly, and low-speed memory for storing the less significant bits (LSBs) that change frequently. This segmentation allows the system to achieve high counter update speeds without requiring entirely high-speed memory, thereby reducing power consumption and cost while maintaining the ability to track high bandwidth traffic.
Solution Approach 2:
The patent applies local quality by assigning different memory technologies to different parts of the counter based on their update characteristics. The MSBs, which rollover infrequently, are stored in high-speed memory, while the LSBs, which update rapidly, are stored in low-speed memory. This localized optimization allows each memory type to be used where it is most effective, reducing overall system cost and power consumption while maintaining high-speed counting capability.
2Measurement precision
If counter width is increased beyond 48-bits to prevent rollover in high speed systems, then measurement precision is improved, but memory depth and cost increase
Solution Approach 1:
The patent segments the wide counter into two parts stored in different memories: the upper bits (MSBs) are stored in high-speed memory with limited depth, and the lower bits (LSBs) are stored in low-speed memory with greater depth. This segmentation allows the system to achieve high measurement precision through wide counters without requiring entirely deep high-speed memory, thereby reducing overall memory cost and power consumption.
Solution Approach 2:
The patent introduces a new dimension to the counter storage architecture by using a hierarchical memory structure with different speed and depth characteristics. Instead of using a single deep high-speed memory, the system distributes counter bits across two memory dimensions: high-speed/low-depth for MSBs and low-speed/high-depth for LSBs. This dimensional differentiation allows the system to achieve both wide counter precision and cost-effective memory usage.
3Productivity
If high speed memory depth is increased to accommodate more flows and wider counters, then productivity is improved, but cost and area requirements increase
Solution Approach 1:
The patent segments the memory requirements by function and speed characteristic: high-speed memory is allocated for MSBs where speed is critical but depth requirements are lower, while low-speed memory is allocated for LSBs where greater depth is needed but speed is less critical. This segmentation enables the system to achieve high productivity for statistics collection across multiple flows without requiring a proportionally large area of expensive high-speed memory.
Solution Approach 2:
The patent changes the speed parameter of the memory subsystem by introducing a two-tier memory architecture. Instead of uniformly using high-speed memory for all counter bits, the system uses high-speed memory only where necessary (for MSBs) and low-speed memory for other portions (LSBs). This parameter change in memory speed distribution reduces the total area of high-speed memory required while maintaining the system's ability to handle high-bandwidth statistics collection.
Data Source
AI summary
A method, a statistics subsystem, and a system use a combination of commercially available high speed memory and high density low speed memory to mitigate cost, space, control, and power issues associated with storing counters for statistics updates, while meeting the growing width and depth needs of multi-hundred gigabit Carrier Class data network devices. The method, statistics subsystem, and system offer a Counter Management Algorithm (CMA) that relies on rollover bits stored within data of counters. An update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory.