Counter-Based Memory Readout for Variable 3D Cell Characteristics
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Solution Overview
Problem
Existing memory devices, particularly 3D arrays of memory cells, face challenges in accurately reading data due to variable electrical characteristics resulting from factors like statistical process variations, cycling events, and resistance drift, which can lead to errors and impractical reliance on error correction mechanisms.
Innovation Solution
A counter-based sense amplifier method is employed to read memory cells, where user data is encoded with a predetermined number of bits and additional parity bits, and a counter stores counting information to ensure a known number of cells in a given logic state, allowing for accurate reading by comparing the counter data with the actual number of logic states during the reading process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional read techniques are used in 3D memory arrays, then the memory device can operate with standard architecture, but reading accuracy deteriorates due to variable electrical characteristics from process variations, cycling events, and resistance drift
Solution Approach 1:
The patent applies preliminary action by pre-programming a predetermined number of counter cells to a first logic state before the read operation. This counter is then used to track and verify the number of memory cells in the array that are in the first logic state, enabling accurate reading despite electrical characteristic variations. The counter is prepared in advance to compensate for potential reading errors.
Solution Approach 2:
The patent implements feedback by using the counter to monitor the number of memory cells in the first logic state during the read operation. The counter's state is fed back to verify whether the read operation successfully retrieved the expected number of cells in the first logic state, allowing for error detection and correction based on the predetermined counter value.
2Measurement precision
If error correction mechanisms are implemented to handle variable electrical characteristics, then reading accuracy improves, but device complexity increases
Solution Approach 1:
The patent simplifies error correction by pre-setting a counter to a predetermined value that represents the expected number of cells in the first logic state. This preliminary configuration eliminates the need for complex post-read error correction algorithms, as the counter provides an immediate reference for verifying read accuracy.
Solution Approach 2:
The counter serves a dual function: it acts as both a read verification mechanism and an error correction reference. The counter's predetermined value automatically provides the basis for detecting and correcting reading errors without requiring external error correction circuits or complex processing, making the system self-verified.
3Reliability
If a counter-based read technique is implemented to improve reading accuracy, then reading reliability improves, but the encoding and read process complexity increases
Solution Approach 1:
The patent reduces process complexity by pre-programming the counter cells to a predetermined value during manufacturing or initialization. This preliminary setup eliminates the need for complex runtime calculations or iterative error correction processes, as the counter is already configured to provide the expected read result reference.
Solution Approach 2:
The patent changes the parameter of the counter cells from generic memory cells to specifically configured counter elements with a predetermined number of cells set to the first logic state. This parameter change enables the counter to inherently provide error detection and correction capabilities without requiring complex additional circuitry or processing steps.
Data Source
AI summary
A method including storing user data in memory cells of a memory array, storing, in a counter associated to the memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data, applying the read voltage to the cells of the counter to read the count data and to provide a target value corresponding to the number of bits in the user data having the first logic value. During the application of the read voltage, the count data and the user data are read simultaneously such that the target value is provided during the reading of the user data. The application of the read voltage is stopped when the number of bits in the user data having the first logic value corresponds to the target value.