High-Speed Counter Module Diagnostics Without Counting Interruption
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Solution Overview
Problem
Existing counter modules lack effective diagnostic capabilities to detect short or open input signals and failures in counting capability without disrupting counting operations, especially when the application is stationary.
Innovation Solution
A Functional Safety Counter Module with test circuitry that allows individual control of counter input signals and firmware algorithms to perform seamless testing and resynchronization of counters without stopping counting operations, using separate firmware algorithms for each counter to detect and adjust for offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diagnostic testing is performed on counter input signals, then detection capability of short or open input signals is improved, but counting operation is disrupted
Solution Approach 1:
The counter module is divided into multiple independent counter channels (e.g., 4 counters). When diagnostic testing is performed, only one counter is taken offline at a time while others continue counting. This segmentation allows testing to be isolated to specific channels, maintaining overall system productivity while enabling comprehensive diagnostic coverage.
Solution Approach 2:
Diagnostic testing is performed periodically on each counter in a sequential manner. The system cycles through testing each counter individually at scheduled intervals rather than continuously blocking all counters. This periodic approach ensures that at any given time, most counters are operational, maintaining high productivity while achieving reliable detection through regular diagnostics.
2Reliability
If counter testing is performed, then diagnostic coverage is improved, but counting accuracy may be compromised due to resynchronization offset
Solution Approach 1:
The system implements feedback mechanisms to detect and correct resynchronization offset. After a counter is taken offline for testing and then restored, the system monitors for offset conditions and applies corrective adjustments. This feedback loop ensures that any loss of synchronization accuracy is detected and corrected, maintaining measurement precision while enabling comprehensive diagnostic testing.
Solution Approach 2:
The system performs preliminary actions to prepare for and mitigate resynchronization issues before they affect counting accuracy. This includes implementing offset detection and correction algorithms that are ready to execute immediately when a counter is restored after testing, preventing accuracy degradation rather than reacting to it after the fact.
3Measurement precision
If individual counter control is implemented for testing, then diagnostic precision is improved, but device complexity increases
Solution Approach 1:
The test circuitry is designed with universal, multi-functional components that can be configured to test any counter channel. Rather than implementing separate dedicated test circuits for each counter, a single versatile test interface is used that can be dynamically assigned to different counters through software control. This reduces hardware complexity while maintaining the ability to precisely control and diagnose individual counters.
Solution Approach 2:
The system uses its own operational counters to assist in testing other counters. When one counter is taken offline for testing, the remaining operational counters continue to run and can provide reference signals or synchronization information that aids the diagnostic process. This self-service approach reduces the need for external test equipment and simplifies the overall test circuitry.
Data Source
AI summary
A Functional Safety Counter Module is provided and it comprises input circuitry, test circuitry, a first microcontroller including a first hardware counter, a second hardware counter, a first storage device that stores a first firmware algorithm code to execute a counter pattern test in order to detect a short open input signal and/or a failure in counting capability of the first microcontroller and a second microcontroller including a third hardware counter, a fourth hardware counter, a second storage device that stores a second firmware algorithm code. The first and second firmware algorithm codes are configured to resynchronize and restore respectively a first counter or a second counter after the counter pattern test and are configured to detect an offset and adjust during a resynchronization process to account for the offset such that to successfully resynchronize two separate resynchronization algorithm codes are used depending on an input frequency of counter signals input to four hardware counters.