Counter-Based Multi-Phase Clock Generation With Stable Phase Difference
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Solution Overview
Problem
Semiconductor devices using phase locked loop circuits for generating multi-phase clocks face issues with large layout area and high power consumption, and the phase difference of multi-phase clocks is susceptible to variations due to external noise, affecting their reliability.
Innovation Solution
A clock generating circuit that uses a pulse generator to produce pulse signals with a consistent phase difference, which are then used by a multi-phase clock generator to produce clocks with equal phase differences, independent of delay cell variations, thereby reducing area and power consumption and ensuring constant phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop circuit is used to generate multi-phase clocks, then multi-phase clocks can be generated, but the layout area increases and power consumption increases
Solution Approach 1:
The patent extracts the essential function of multi-phase clock generation from the complex phase locked loop circuit. By using a simple counter circuit that counts clock cycles and generates pulse signals at specific count values, the invention isolates only the necessary functionality while eliminating unnecessary components, thereby reducing layout area while maintaining the ability to generate multi-phase clocks with accurate phase differences
Solution Approach 2:
The patent uses a digital counting approach where the counter circuit copies the reference clock signal multiple times and generates pulse signals at predetermined intervals based on counting. This digital copying method replaces the analog delay cell structure, achieving the same multi-phase clock generation function with significantly reduced area and improved noise immunity
2Reliability
If a phase locked loop circuit with delay cells is used to generate multi-phase clocks, then multi-phase clocks can be generated, but power consumption increases
Solution Approach 1:
The patent extracts only the essential timing generation function from the phase locked loop circuit, eliminating power-consuming components such as voltage controlled oscillators, charge pumps, and loop filters. The simplified counter-based circuit consumes significantly less power while maintaining the ability to generate multi-phase clocks with accurate phase relationships
Solution Approach 2:
The patent replaces expensive, power-consuming analog delay cells with simple digital counter circuits that use minimal power. The counter circuit generates pulse signals by counting clock cycles and producing outputs at specific count values, achieving the same function with much lower power consumption suitable for mobile and battery-powered devices
3Reliability
If delay cells are used to determine phase difference of multi-phase clocks, then multi-phase clocks can be generated, but the phase difference varies due to external noise
Solution Approach 1:
The patent replaces the mechanical/analog delay cell system with a digital counting system. Instead of using physical delay elements whose delay amounts vary with noise and temperature, the invention uses a counter circuit that counts discrete clock cycles and generates pulse signals at predetermined count values. This digital approach eliminates sensitivity to external noise and ensures constant phase differences
Solution Approach 2:
The patent changes the fundamental parameter used to determine phase difference from analog delay time (which is noise-sensitive) to digital count values (which are noise-immune). By setting the phase difference based on integer multiples of the reference clock period through counting, the system achieves high precision and stability that is independent of external noise, temperature, and voltage variations
Data Source
AI summary
A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.