Counter-Based Read Clock for Stacked Memory Duty Cycle Distortion
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Solution Overview
Problem
In stacked semiconductor memory devices, duty cycle distortion of clock signals over long signal paths between the interface die and core dies leads to timing alignment issues during read and write operations, affecting data transmission reliability.
Innovation Solution
Implementing a counter-based read clock system where the interface die generates a counter-based read clock that is synchronized with the read command, reducing the need for replica delay circuits and minimizing distortion by operating in a faster timing domain, thus ensuring predictable data timing without passing through lengthy signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are transmitted through long signal paths between interface die and core dies, then timing synchronization can be achieved, but duty cycle distortion occurs affecting reliability
Solution Approach 1:
The patent extracts the clock signal generation function from the interface die and relocates it to the core die. This removes the clock signal from the long transmission path through TSVs, eliminating the source of duty cycle distortion while maintaining timing synchronization through local clock generation based on command signals received from the interface die.
2Manufacturing precision
If replica delay circuits are used to compensate for signal path delays, then timing alignment can be improved, but device complexity increases
Solution Approach 1:
Instead of using complex replica delay circuits to compensate for delays in the traditional approach (interface die to core die), the patent inverts the approach by generating the clock locally at the core die. This eliminates the need for delay compensation circuits while achieving the same timing alignment goal.
3Reliability
If clock signals are generated at interface die and transmitted to core dies, then timing control can be maintained, but signal path length increases causing distortion
Solution Approach 1:
The clock signal generation is extracted from the interface die and placed locally in the core die. This eliminates the long transmission path for the clock signal while maintaining timing control accuracy, as the clock is generated locally based on command signals received from the interface die.
Data Source
AI summary
Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.