Counter Readout Circuit for Common-Timing Multi-Counter Output
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Solution Overview
Problem
Existing counter readout circuits fail to read out counter values from multiple counters at a common timing, leading to inefficiencies and increased circuit size due to the use of buffers, which raises manufacturing costs and footprint.
Innovation Solution
A counter readout circuit with a plurality of counter registers and an output data computing unit that allows for the selection of a counter register and computes the counter value by adding the total clock count from a common first timing to a second timing, enabling simultaneous readout of counter values across all counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If counter values are read out sequentially from multiple counters at different timings, then the readout operation can be completed, but the counter values cannot be read out at a common timing and buffers are required increasing circuit size
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the total clock count from a common first timing to each counter's second timing in advance. This allows the counter values to be read out at synchronized timings without requiring buffers, as the timing compensation data is prepared beforehand. The output data computing unit uses this pre-stored clock count information to compute the final counter values at the common readout timing.
Solution Approach 2:
The patent introduces an intermediary element - the total clock count information - that mediates between the different counter timings and the common readout timing. By adding this intermediate timing parameter to each counter value, the system achieves synchronous readout without requiring physical buffers to hold counter values until their respective readout times.
2Measurement precision
If buffers are used to enable simultaneous readout of counter values, then common timing readout is achieved, but manufacturing costs and footprint increase
Solution Approach 1:
The patent extracts the buffer component from the system by replacing it with a computational approach. Instead of using physical buffers to store and synchronize counter values, the invention extracts only the essential timing information (total clock count) and uses computation to achieve the same synchronization effect, thereby eliminating the need for expensive buffer hardware and reducing manufacturing costs.
Solution Approach 2:
The patent applies mechanics substitution by replacing the mechanical buffer storage system with a computational system. Rather than physically storing counter values in buffers until readout, the invention uses arithmetic computation (adding total clock count to counter values) to achieve timing synchronization, substituting a computational mechanism for a physical storage mechanism.
3Measurement precision
If buffers are used to enable simultaneous readout of counter values, then common timing readout is achieved, but circuit footprint increases
Solution Approach 1:
The patent uses copying by creating a computational copy of the timing information (total clock count) rather than physically copying and storing counter values in buffers. The total clock count represents the timing relationship and is used to compute the final synchronized counter values, achieving the same effect as buffers but with minimal circuit footprint.
Solution Approach 2:
The patent transitions from a spatial dimension (using physical buffers that occupy circuit area) to a computational dimension (using arithmetic operations on timing data). By moving the synchronization function from the physical storage domain to the computational processing domain, the invention achieves timing synchronization without increasing circuit footprint.
Data Source
AI summary
A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.