Counter-Based Sense Amplifier Reading for Drifted 3D Memory Cells
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Solution Overview
Problem
Existing memory devices, particularly phase change memory (PCM) cells, face challenges due to resistivity drift over time, leading to inaccurate reading of threshold voltage distributions and reduced reliability, especially in 3D arrays, where manufacturing variations and operational drift cause non-uniform electrical characteristics.
Innovation Solution
A counter-based sense amplifier method is employed, involving a Bit Flip operation during programming to ensure at least 50% of cells are programmed with a specific logic value, followed by a counter-based reading algorithm that uses a fast biasing voltage ramp and ECC-protected counters to accurately determine the number of cells with that logic state, reducing the applied voltage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reading methods are used in 3D memory arrays, then reading operations can be performed, but read reliability deteriorates due to resistivity drift and manufacturing variations causing non-uniform electrical characteristics
Solution Approach 1:
The patent applies parameter changes by using a ramped biasing voltage that increases over time during the reading operation, rather than applying a fixed voltage. This dynamic voltage adjustment compensates for resistivity drift and manufacturing variations, allowing accurate determination of logic states despite non-uniform electrical characteristics across memory cells
Solution Approach 2:
The patent implements feedback through a counter-based reading algorithm that continuously monitors the number of triggered memory cells during the ramped voltage operation. The reading process dynamically adjusts based on feedback from the counter, comparing the triggered cell count against expected values to accurately determine stored logic states even when electrical characteristics vary
2Measurement precision
If higher biasing voltages are applied to improve reading accuracy, then measurement precision improves, but power consumption and stress on memory cells increase
Solution Approach 1:
The patent uses dynamics by implementing a time-varying ramped voltage waveform instead of a static high voltage. The biasing voltage starts low and gradually increases, allowing the system to achieve measurement precision through the dynamic scanning process rather than applying continuously high voltage, thereby reducing overall power consumption and cell stress
Solution Approach 2:
The patent applies periodic action through the ramped voltage waveform that systematically increases over time during the reading operation. This periodic voltage application allows the system to gather information across different voltage levels, achieving accurate logic state determination while limiting the duration and magnitude of high voltage exposure to reduce power consumption
Data Source
AI summary
Methods, systems, and devices for a counter-based sense amplifier method for memory cells are described. The described techniques provide for a memory system to store, in a counter associated with an array of memory cells, a value indicating a quantity of memory cells in the array having a predetermined logic value. The memory system may perform a read operation to read the data stored in the array of memory cells by applying a ramping bias voltage and may count the quantity of memory cells having the predetermined logic value during the read operation. The memory system may stop the read operation when the memory system identifies a quantity of memory cells having the predetermined logic value that is equal to the value stored to the counter.