Counter Synchronization Using Independent Clocks Without Count Jumps
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Solution Overview
Problem
Existing synchronization methods between semiconductor devices either rely on a shared clock source, leading to failure when the oscillator or clock oscillation circuit fails, or use different clocks, resulting in discontinuous changes to timer values during synchronization.
Innovation Solution
A semiconductor device configuration that includes a clock oscillator, counter, match flag register, match output terminal, match input terminal, and a reset circuit, allowing synchronization without discontinuous changes to the counter's count value by resetting both devices when their match flag values coincide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shared clock source is used for synchronization between semiconductor devices, then synchronization is achieved, but the system becomes vulnerable to complete failure when the oscillator or clock oscillation circuit fails
Solution Approach 1:
The patent divides the clock source into separate independent oscillators for each semiconductor device. Instead of using a single shared clock source, each device has its own oscillator, allowing independent operation and preventing single-point failure. This segmentation enables the system to maintain functionality even when one oscillator fails.
Solution Approach 2:
The patent changes the parameter of clock source configuration from shared to independent. By modifying the system architecture to use separate oscillators with different frequencies, the patent achieves both synchronization capability and fault tolerance, resolving the contradiction between reliability and adaptability.
2Adaptability or versatility
If different clock sources are used for each semiconductor device, then clock source independence and fault tolerance are achieved, but discontinuous changes occur in timer values during synchronization
Solution Approach 1:
The patent introduces a synchronization signal as an intermediary mechanism between devices using different clock sources. This synchronization signal coordinates the timer values across devices, ensuring continuous and consistent timing information is maintained despite the use of independent oscillators with different frequencies.
Solution Approach 2:
The patent implements feedback mechanisms where timer values and synchronization status are monitored and adjusted. By continuously comparing timer states and providing feedback control, the system maintains continuous timer values across synchronization events even when using independent clock sources.
3Reliability
If timer values are corrected to coincide during synchronization, then synchronization is achieved, but the count value becomes discontinuous
Solution Approach 1:
The patent employs dynamic adjustment mechanisms that allow timer values to be synchronized without abrupt discontinuities. By using dynamic control of the synchronization process and gradual adjustment of count values, the system achieves accurate synchronization while maintaining continuity in the count sequence.
Data Source
AI summary
In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor device 1 includes a clock oscillator 2, a counter 3 configured to count the number of clocks, a periodic register 4 in which a value corresponding to a period for synchronization is set, a comparison circuit 5 configured to compare the count value in the counter 3 with the set value in the periodic register 4, a match flag register 6 in which a predetermined value is set when the count value coincides with the set value, a match output terminal 7 configured to output the value in the match flag register 6 from the own semiconductor device, a match input terminal 8 to which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counter 3 and the match flag register 6 when both the value in the match flag register 6 of the own semiconductor device and the value input to the match input terminal 8 become a predetermined value.