Counter-Based SYSREF Synchronization for Cascaded Clock Dividers
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Solution Overview
Problem
As device input clock frequencies increase, ensuring proper setup and hold margins for the latched SYSREF pulse across variations in process, voltage, and temperature becomes challenging, especially when the SYSREF and device clock are asynchronous, leading to uncertainty in the periodicity of the latched SYSREF pulse with respect to the device clock in cascaded clock divider systems.
Innovation Solution
A system comprising an input flip-flop, a counter, and cascaded clock dividers where the counter counts device clock pulses initiated by the latched SYSREF signal, generating an internal SYSREF signal that synchronizes the clock dividers, eliminating the need for external SYSREF pulses and reducing coupling with other signals, thus maintaining periodicity and phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device input clock frequency is increased, then the productivity and performance of the system is improved, but it becomes difficult to guarantee proper setup and hold margins at the flip-flop that latches SYSREF across variations in process, voltage, and temperature
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal SYSREF pulse widths and timing parameters in lookup tables before operation. When the device clock frequency changes, the system quickly retrieves pre-computed timing parameters that guarantee proper setup and hold margins, avoiding the need for complex real-time calculations and ensuring reliable latching across PVT variations.
Solution Approach 2:
The patent dynamically adjusts SYSREF pulse width and timing parameters based on the device clock frequency and operating conditions. By changing these parameters adaptively - using wider pulses at higher frequencies and adjusting timing margins - the system maintains reliable synchronization while supporting high clock frequencies. This is achieved through frequency-dependent parameter selection from lookup tables or adaptive timing control circuits.
2Adaptability or versatility
If the SYSREF and device clock are asynchronous, then the system has greater flexibility in clock source selection, but the periodicity of the latched SYSREF pulse cannot be guaranteed with respect to the device clock
Solution Approach 1:
The patent introduces an intermediary mechanism - a counter synchronized to the device clock that generates periodic SYSREF_OUT pulses based on the latched SYSREF signal. This counter acts as a mediator between the asynchronous external SYSREF input and the internal clock distribution network, converting the irregular latched SYSREF signal into a periodic output that is precisely aligned with the device clock cycles, thus guaranteeing periodicity while maintaining asynchronous input flexibility.
Solution Approach 2:
The system uses feedback by monitoring the device clock cycles and using a counter that increments on each clock cycle. The counter generates SYSREF_OUT pulses at predetermined intervals based on feedback from the clock divider outputs, ensuring that the periodicity is maintained with respect to the device clock even when the input SYSREF is asynchronous. This feedback mechanism allows the system to adapt to different clock frequencies while maintaining stable periodic output.
3Reliability
If multiple external SYSREF pulses are used to synchronize cascaded clock dividers, then all clock dividers can be synchronized, but the coupling with other signals increases and power consumption rises
Solution Approach 1:
The patent extracts the SYSREF pulse generation function from external sources and implements it internally using a counter that generates SYSREF_OUT pulses based on the latched SYSREF signal and device clock. This internal generation eliminates the need for multiple external SYSREF pulses to reach different clock dividers, reducing external signal coupling requirements and allowing clock dividers to be powered down when not needed, thus reducing power consumption while maintaining synchronization reliability.
Solution Approach 2:
The system applies self-service by using its own internal resources - the latched SYSREF signal and device clock - to generate the synchronization pulses needed for clock dividers. The counter internally generates SYSREF_OUT pulses without requiring external SYSREF inputs for each clock divider, making the system self-sufficient for synchronization. This reduces external coupling and enables power management of clock dividers since they can be synchronized on-demand using internally generated pulses.
Data Source
AI summary
A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.